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Merge pull request #1318 from coreyqh/ccov

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100% fctrl and Hazard code coverage
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David Harris 2025-04-03 10:24:12 -07:00 • committed by GitHub
commit dd726079a4
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3 changed files with 12 additions and 4 deletions
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7
sim/questa/coverage-exclusions-rv64gc.do
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@ -55,6 +55,9 @@ coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineN
coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ${SRC}/fpu/postproc/flags.sv "assign Underflow"] -item e 1 -fecexprrow 22
# Convert int to fp will never underflow
coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [GetLineNum ${SRC}/fpu/postproc/cvtshiftcalc.sv "assign CvtResUf"] -item e 1 -fecexprrow 4
# without Q support, the FMT field is guaranteed to be 00, 01, or 10
coverage exclude -scope /dut/core/fpu/fpu/fctrl -linerange [GetLineNum ${SRC}/fpu/fctrl.sv "fmv int to fp"] -item 1 3 5
coverage exclude -scope /dut/core/fpu/fpu/fctrl -linerange [GetLineNum ${SRC}/fpu/fctrl.sv "fmv fp to int"] -item 1 3 5
##################
# Cache Exclusions
@ -406,6 +409,10 @@ coverage exclude -srcfile priorityonehot.sv
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ${SRC}/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ${SRC}/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
# StallD always equals StallF so LatestUnstalledD is always 0
coverage exclude -scope /dut/core/hzu -linerange [GetLineNum ${SRC}/hazard/hazard.sv "StallD always equals StallF"] -item 1 4
coverage exclude -scope /dut/core/hzu -linerange [GetLineNum ${SRC}/hazard/hazard.sv "coverage tag: LatestUnstalledD always 0"] -item e 1 -fecexprrow 2
####################
# Privileged
####################

4
src/fpu/fctrl.sv
View file

@ -154,7 +154,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)
ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0_0_0; // fclass
else if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin
if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01))
if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01)) // coverage-tag: fmv fp to int
ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_0_0; // fmv.x.w/d/h fp to int register (double only in RV64)
end else if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct7D[1:0] == 2'b01 & Funct3D == 3'b000 & Rs2D == 5'b00001)
ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.d (Zfa)
@ -164,7 +164,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.q (Zfa)
// coverage on
7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin
if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01))
if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01)) // coverage-tag: fmv int to fp
ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_0_0; // fmv.w/d/h.x int to fp reg (double only in RV64)
end else if (P.ZFA_SUPPORTED & Funct3D == 3'b000 & Rs2D == 5'b00001)
ControlsD = `FCTRLW'b1_0_00_00_111_0_0_0_1_0; // fli (Zfa)

5
src/hazard/hazard.sv
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@ -101,13 +101,14 @@ module hazard (
assign StallW = StallWCause;
// detect the first stage that is not stalled
assign LatestUnstalledD = ~StallD & StallF;
assign LatestUnstalledD = ~StallD & StallF; // coverage tag: StallD always equals StallF
assign LatestUnstalledE = ~StallE & StallD;
assign LatestUnstalledM = ~StallM & StallE;
assign LatestUnstalledW = ~StallW & StallM;
// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
assign FlushD = LatestUnstalledD | FlushDCause;
assign FlushD = LatestUnstalledD | FlushDCause; // coverage tag: LatestUnstalledD always 0
assign FlushE = LatestUnstalledE | FlushECause;
assign FlushM = LatestUnstalledM | FlushMCause;
assign FlushW = LatestUnstalledW | FlushWCause;