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removed rv64gc python cache script, updated testbench.sv

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SadhviNarayanan 2025-05-10 13:36:10 -07:00
parent 75dcf6801c
commit df1a787c60
3 changed files with 4 additions and 101 deletions
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testbench/testbench.sv
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@ -86,7 +86,7 @@ module testbench;
logic ResetMem;
// Variables that can be overwritten with $value$plusargs at start of simulation
string TEST, ElfFile;
string TEST, ElfFile, sim_log_prefix;
integer INSTR_LIMIT;
// DUT signals
@ -291,7 +291,7 @@ module testbench;
logic ResetCntRst;
logic CopyRAM;
string sim_log_prefix, signame, elffilename, memfilename, bootmemfilename, uartoutfilename, pathname;
string signame, elffilename, memfilename, bootmemfilename, uartoutfilename, pathname;
integer begin_signature_addr, end_signature_addr, signature_size;
integer uartoutfile;