mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-22 12:57:23 -04:00
Merge pull request #849 from davidharrishmc/dev
lint cleanup and divider optimization
This commit is contained in:
Rose Thompson
GitHub
commit
e1fc44a5bf
11 changed files with 50 additions and 34 deletions
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@ -12,7 +12,7 @@ NC='\033[0m' # No Color
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fails=0
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if [ "$1" == "--nightly" ]; then
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configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) # fdqh_rv64gc
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configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i)
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derivconfigs=`ls $WALLY/config/deriv`
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for entry in $derivconfigs
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do
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@ -21,7 +21,7 @@ if [ "$1" == "--nightly" ]; then
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fi
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done
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else
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configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i ) # add fdqh_rv64gc when working
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configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc)
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fi
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for config in ${configs[@]}; do
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@ -388,10 +388,23 @@ VIRTMEM_SUPPORTED 0
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deriv nodcache_rv32gc rv32gc
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DCACHE_SUPPORTED 0
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D_SUPPORTED 0
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ZALRSC_SUPPORTED 0
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ZAAMO_SUPPORTED 0
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ZICBOM_SUPPORTED 0
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ZICBOZ_SUPPORTED 0
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VIRTMEM_SUPPORTED 0
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# nocache_rv32gc must also disable several features incompatible with no cache
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deriv nocache_rv32gc rv32gc
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ICACHE_SUPPORTED 0
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DCACHE_SUPPORTED 0
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D_SUPPORTED 0
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ZALRSC_SUPPORTED 0
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ZAAMO_SUPPORTED 0
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ZICBOM_SUPPORTED 0
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ZICBOZ_SUPPORTED 0
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VIRTMEM_SUPPORTED 0
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deriv noicache_rv64gc rv64gc
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ICACHE_SUPPORTED 0
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@ -61,7 +61,6 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
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logic [P.DIVb+3:0] D; // Iterator Divisor
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logic [P.DIVb:0] FirstU, FirstUM; // Intermediate result values
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logic [P.DIVb+1:0] FirstC; // Step tracker
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logic Firstun; // Quotient selection
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logic WZeroE; // Early termination flag
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logic [P.DURLEN-1:0] CyclesE; // FSM cycles
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logic SpecialCaseM; // Divide by zero, square root of negative, etc.
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@ -89,11 +88,11 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
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fdivsqrtiter #(P) fdivsqrtiter( // CSA Iterator
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.clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .D,
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.FirstU, .FirstUM, .FirstC, .Firstun, .FirstWS(WS), .FirstWC(WC));
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.FirstU, .FirstUM, .FirstC, .FirstWS(WS), .FirstWC(WC));
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fdivsqrtpostproc #(P) fdivsqrtpostproc( // Postprocessor
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.clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC,
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.SqrtE, .Firstun, .SqrtM, .SpecialCaseM,
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.SqrtE, .SqrtM, .SpecialCaseM,
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.UmM, .WZeroE, .DivStickyM,
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// Int-specific
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.IntNormShiftM, .ALTBM, .AsM, .BsM, .BZeroM, .W64M, .RemOpM(Funct3M[1]), .AM,
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@ -35,7 +35,6 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
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input logic [P.DIVb+3:0] X, D, // Q4.DIVb
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output logic [P.DIVb:0] FirstU, FirstUM, // U1.DIVb
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output logic [P.DIVb+1:0] FirstC, // Q2.DIVb
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output logic Firstun,
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output logic [P.DIVb+3:0] FirstWS, FirstWC // Q4.DIVb
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);
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@ -119,6 +118,5 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
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assign FirstU = U[0];
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assign FirstUM = UM[0];
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assign FirstC = C[0];
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assign Firstun = un[0];
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endmodule
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@ -35,7 +35,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
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input logic [P.DIVb:0] FirstU, FirstUM, // U1.DIVb
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input logic [P.DIVb+1:0] FirstC, // Q2.DIVb
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input logic SqrtE,
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input logic Firstun, SqrtM, SpecialCaseM,
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input logic SqrtM, SpecialCaseM,
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input logic [P.XLEN-1:0] AM, // U/Q(XLEN.0)
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input logic RemOpM, ALTBM, BZeroM, AsM, BsM, W64M,
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input logic [P.DIVBLEN-1:0] IntNormShiftM,
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@ -71,7 +71,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
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mux2 #(P.DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
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csa #(P.DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
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aplusbeq0 #(P.DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
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assign WZeroE = weq0E|(wfeq0E & Firstun);
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assign WZeroE = weq0E | wfeq0E;
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end else begin
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assign WZeroE = weq0E;
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end
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@ -233,8 +233,9 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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flopen #(P.XLEN) srcareg(clk, IFDivStartE, AE, AM);
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if (P.XLEN==64)
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flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M);
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else assign W64M = 0;
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end else
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assign {ALTBM, W64M, AsM, BsM, BZeroM, AM, IntNormShiftM} = 0;
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assign {ALTBM, W64M, AsM, BsM, BZeroM, AM, IntNormShiftM} = '0;
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endmodule
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@ -134,6 +134,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
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assign OutFmt = IntToFp|~CvtOp ? Fmt : (OpCtrl[1:0] == P.FMT);
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else if (P.FPSIZES == 3 | P.FPSIZES == 4)
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assign OutFmt = IntToFp|~CvtOp ? Fmt : OpCtrl[1:0];
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else assign OutFmt = 0; // FPSIZES = 1
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///////////////////////////////////////////////////////////////////////////////
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// Normalization
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@ -38,12 +38,15 @@ module zknde64 import cvw::*; #(parameter cvw_t P) (
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if (P.ZKND_SUPPORTED) // ZKND supports aes64ds, aes64dsm, aes64im
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aes64d aes64d(.rs1(A), .rs2(B), .finalround(ZKNSelect[2]), .aes64im(ZKNSelect[3]), .result(aes64dRes)); // decode AES
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else assign aes64dRes = '0;
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if (P.ZKNE_SUPPORTED) begin // ZKNE supports aes64es, aes64esm
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aes64e aes64e(.rs1(A), .rs2(B), .finalround(ZKNSelect[2]), .Sbox0Out, .SboxEIn, .result(aes64eRes));
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mux2 #(32) sboxmux(SboxEIn, SboxKIn, ZKNSelect[1], Sbox0In);
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end else
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end else begin
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assign aes64eRes = '0;
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assign Sbox0In = SboxKIn;
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end
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// One S Box is always needed for aes64ks1i and is also needed for aes64e if that is supported. Put it at the top level to allow sharing
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aessbox32 sbox(Sbox0In, Sbox0Out); // Substitute bytes of value obtained for tmp2 using Rijndael sbox
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@ -144,7 +144,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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logic DTLBMissM; // DTLB miss causes HPTW walk
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logic DTLBWriteM; // Writes PTE and PageType to DTLB
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logic DataUpdateDAM; // DTLB hit needs to update dirty or access bits
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logic LSULoadAccessFaultM; // Load acces fault
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logic LSUStoreAmoAccessFaultM; // Store access fault
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logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle
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@ -194,13 +193,13 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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if(P.VIRTMEM_SUPPORTED) begin : hptw
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hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrUpdateAF, .ITLBWriteF,
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.DTLBMissOrUpdateDAM, .DTLBWriteM, .DataUpdateDAM,
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.DTLBMissOrUpdateDAM, .DTLBWriteM,
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.FlushW, .DCacheBusStallM, .SATP_REGW, .PCSpillF,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_ADUE, .PrivilegeModeW,
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.ReadDataM(ReadDataM[P.XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
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.WriteDataM(WriteDataZM), .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
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.IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
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.IHAdrM, .HPTWStall, .SelHPTW,
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.IHAdrM, .HPTWStall, .SelHPTW,
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.IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM,
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.LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultF,
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.LoadPageFaultM, .StoreAmoPageFaultM, .LSULoadPageFaultM, .LSUStoreAmoPageFaultM, .HPTWInstrPageFaultF
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@ -236,6 +235,8 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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if(P.ZICSR_SUPPORTED == 1) begin : dmmu
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logic DisableTranslation; // During HPTW walk or D$ flush disable virtual memory address translation
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logic WriteAccessM;
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logic DataUpdateDAM; // DTLB hit needs to update dirty or access bits
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assign DisableTranslation = SelHPTW | FlushDCacheM;
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assign WriteAccessM = PreLSURWM[0];
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mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0))
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@ -245,7 +246,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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.PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM),
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.InstrAccessFaultF(), .LoadAccessFaultM(LSULoadAccessFaultM),
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.StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM), .InstrPageFaultF(), .LoadPageFaultM(LSULoadPageFaultM),
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.StoreAmoPageFaultM(LSUStoreAmoPageFaultM),
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.StoreAmoPageFaultM(LSUStoreAmoPageFaultM),
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.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
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.UpdateDA(DataUpdateDAM), .CMOpM(CMOpM),
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.AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0),
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@ -49,7 +49,6 @@ module hptw import cvw::*; #(parameter cvw_t P) (
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input logic ITLBMissOrUpdateAF,
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input logic DTLBMissOrUpdateDAM,
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input logic FlushW,
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input logic DataUpdateDAM,
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output logic [P.XLEN-1:0] PTE, // page table entry to TLBs
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output logic [1:0] PageType, // page type to TLBs
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output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
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@ -110,6 +110,7 @@ module testbench;
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logic Validate;
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logic SelectTest;
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logic TestComplete;
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logic PrevPCZero;
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initial begin
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// look for arguments passed to simulation, or use defaults
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@ -354,15 +355,6 @@ module testbench;
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$display("Benchmark: coremark is done.");
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$stop;
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end
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if (P.ZICSR_SUPPORTED & dut.core.ifu.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.ieu.InstrValidM) begin
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$display("Program fetched illegal instruction 0x00000000 from address 0x00000000. Might be fault with no fault handler.");
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//$stop; // presently wally32/64priv tests trigger this for reasons not yet understood.
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end
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// modifications 4/3/24 kunlin & harris to speed up Verilator
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// For some reason, Verilator runs ~100x slower when these SelectTest and Validate codes are in the posedge clk block
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//end // added
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//always @(posedge SelectTest) // added
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if(SelectTest) begin
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if (riscofTest) begin
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memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
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@ -402,6 +394,7 @@ module testbench;
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always @(posedge Validate) // added
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`endif
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if(Validate) begin
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if (PrevPCZero) totalerrors = totalerrors + 1; // error if PC is stuck at zero
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if (TEST == "buildroot")
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$fclose(uartoutfile);
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if (TEST == "embench") begin
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@ -632,8 +625,10 @@ module testbench;
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loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename, TEST);
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// track the current function or global label
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FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset),
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.clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
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if (DEBUG > 0 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : FunctionName
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FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset),
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.clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
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end
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// Append UART output to file for tests
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if (P.UART_SUPPORTED) begin: uart_logger
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@ -652,12 +647,18 @@ module testbench;
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// 1. jump to self loop (0x0000006f)
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// 2. a store word writes to the address "tohost"
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// 3. or PC is stuck at 0
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always_comb begin
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TestComplete = ((InstrM == 32'h6f) & dut.core.InstrValidM ) |
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((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW" ) |
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(FunctionName.PCM == 4 & dut.core.ieu.c.InstrValidM);
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end
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always @(posedge clk) begin
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// if (reset) PrevPCZero <= 0;
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// else if (dut.core.InstrValidM) PrevPCZero <= (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0);
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TestComplete <= ((InstrM == 32'h6f) & dut.core.InstrValidM ) |
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((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW"); // |
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// (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero));
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// if (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero)
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// $error("Program fetched illegal instruction 0x00000000 from address 0x00000000 twice in a row. Usually due to fault with no fault handler.");
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end
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DCacheFlushFSM #(P) DCacheFlushFSM(.clk, .start(DCacheFlushStart), .done(DCacheFlushDone));
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if(P.ZICSR_SUPPORTED) begin
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