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https://github.com/openhwgroup/cvw.git
synced 2025-04-22 12:57:23 -04:00
Add number of mismatches exit code to cachesim scripts
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parent
e48d577545
commit
e6ddebde72
2 changed files with 20 additions and 8 deletions
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@ -192,7 +192,7 @@ class Cache:
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return self.__str__()
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if __name__ == "__main__":
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def main():
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parser = argparse.ArgumentParser(description="Simulates a L1 cache.")
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parser.add_argument('numlines', type=int, help="The number of lines per way (a power of 2)", metavar="L")
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parser.add_argument('numways', type=int, help="The number of ways (a power of 2)", metavar='W')
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@ -206,7 +206,7 @@ if __name__ == "__main__":
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args = parser.parse_args()
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cache = Cache(args.numlines, args.numways, args.addrlen, args.taglen)
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extfile = os.path.expanduser(args.file)
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nofails = True
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mismatches = 0
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if args.perf:
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hits = 0
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@ -268,7 +268,7 @@ if __name__ == "__main__":
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if not result == lninfo[2]:
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print("Result mismatch at address", lninfo[0]+ ". Wally:", lninfo[2]+", Sim:", result)
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nofails = False
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mismatches += 1
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if args.dist:
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percent_loads = str(round(100*loads/totalops))
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percent_stores = str(round(100*stores/totalops))
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@ -279,5 +279,9 @@ if __name__ == "__main__":
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ratio = round(hits/misses,3)
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print("There were", hits, "hits and", misses, "misses. The hit/miss ratio was", str(ratio)+".")
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if nofails:
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print("SUCCESS! There were no mismatches between Wally and the sim.")
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if mismatches == 0:
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print("SUCCESS! There were no mismatches between Wally and the sim.")
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return mismatches
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if __name__ == '__main__':
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exit(main())
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@ -29,6 +29,7 @@
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################################################################################################
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import os
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import argparse
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import subprocess
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# NOTE: make sure testbench.sv has the ICache and DCache loggers enabled!
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# This does not check the test output for correctness, run regression for that.
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@ -58,16 +59,17 @@ tests64gc = ["arch64i"]
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cachetypes = ["ICache", "DCache"]
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simdir = os.path.expandvars("$WALLY/sim")
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if __name__ == '__main__':
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def main():
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parser = argparse.ArgumentParser(description="Runs the cache simulator on all rv64gc test suites")
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parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio")
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parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
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parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="verilator")
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args = parser.parse_args()
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simargs = "-GI_CACHE_ADDR_LOGGER=1\\\'b1 -GD_CACHE_ADDR_LOGGER=1\\\'b1"
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testcmd = "wsim --sim " + args.sim + " rv64gc {} --args \"" + simargs + "\" > /dev/null"
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cachecmd = "CacheSim.py 64 4 56 44 -f {}"
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mismatches = 0
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if args.perf:
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cachecmd += " -p"
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@ -83,5 +85,11 @@ if __name__ == '__main__':
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os.system(testcmd.format(test))
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for cache in cachetypes:
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print(f"{bcolors.OKCYAN}Running the", cache, f"simulator.{bcolors.ENDC}")
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os.system(cachecmd.format(args.sim+"/"+cache+".log"))
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result = subprocess.run(cachecmd.format(args.sim+"/"+cache+".log"), shell=True)
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mismatches += result.returncode
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print()
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return mismatches
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if __name__ == '__main__':
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exit(main())
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