mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-24 13:57:07 -04:00
Moved shared constants into per-processor config and removed wally-constants
This commit is contained in:
David Harris
parent
234860d4e5
commit
e7883775f3
12 changed files with 231 additions and 161 deletions
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@ -134,3 +134,16 @@
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`define HPTW_WRITES_SUPPORTED 1
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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// Memory synthesis configuration
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`define USE_SRAM 0
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@ -143,3 +143,16 @@
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`define HPTW_WRITES_SUPPORTED 1
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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// Memory synthesis configuration
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`define USE_SRAM 0
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@ -137,3 +137,16 @@
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`define BPRED_SIZE 10
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`define HPTW_WRITES_SUPPORTED 0
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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// Memory synthesis configuration
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`define USE_SRAM 0
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@ -136,3 +136,16 @@
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`define BPRED_SIZE 10
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`define HPTW_WRITES_SUPPORTED 0
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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// Memory synthesis configuration
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`define USE_SRAM 0
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@ -137,3 +137,16 @@
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`define BPRED_SIZE 10
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`define HPTW_WRITES_SUPPORTED 0
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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// Memory synthesis configuration
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`define USE_SRAM 0
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@ -136,3 +136,16 @@
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`define BPRED_SIZE 10
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`define HPTW_WRITES_SUPPORTED 0
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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// Memory synthesis configuration
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`define USE_SRAM 0
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@ -139,3 +139,16 @@
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`define BPRED_SIZE 10
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`define HPTW_WRITES_SUPPORTED 0
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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// Memory synthesis configuration
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`define USE_SRAM 0
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@ -139,3 +139,16 @@
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`define BPRED_SIZE 10
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`define HPTW_WRITES_SUPPORTED 0
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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// Memory synthesis configuration
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`define USE_SRAM 0
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@ -139,3 +139,16 @@
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`define BPRED_SIZE 10
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`define HPTW_WRITES_SUPPORTED 0
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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// Memory synthesis configuration
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`define USE_SRAM 0
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@ -1,148 +0,0 @@
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//////////////////////////////////////////
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// wally-constants.vh
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//
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// Written: tfleming@hmc.edu 4 March 2021
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// Modified: Kmacsaigoren@hmc.edu 31 May 2021
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// Added constants for checking sv mode and changed existing constants to accomodate
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// both sv48 and sv39
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//
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// Purpose: Specify constants nexessary for different memory virtualization modes.
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// These are specific to sv49, defined in section 4.5 of the privileged spec.
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// However, despite different constants for different modes, the hardware helps distinguish between
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// each mode.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// constants defining different privilege modes
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// defined in Table 1.1 of the privileged spec
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`define M_MODE (2'b11)
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`define S_MODE (2'b01)
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`define U_MODE (2'b00)
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// Virtual Memory Constants
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`define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9)
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`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS))
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`define PPN_BITS (`XLEN==32 ? 22 : 44)
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`define PA_BITS (`XLEN==32 ? 34 : 56)
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`define SVMODE_BITS (`XLEN==32 ? 1 : 4)
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`define ASID_BASE (`XLEN==32 ? 22 : 44)
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`define ASID_BITS (`XLEN==32 ? 9 : 16)
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// constants to check SATP_MODE against
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// defined in Table 4.3 of the privileged spec
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`define NO_TRANSLATE 0
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`define SV32 1
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`define SV39 8
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`define SV48 9
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// macros to define supported modes
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`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
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`define B_SUPPORTED ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)) // not based on MISA
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`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
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`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
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`define E_SUPPORTED ((`MISA >> 4) % 2 == 1)
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`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
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`define I_SUPPORTED ((`MISA >> 8) % 2 == 1)
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`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
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`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1)
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`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
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`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
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// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
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// logarithm of XLEN, used for number of index bits to select
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`define LOG_XLEN (`XLEN == 32 ? 5 : 6)
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// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
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`define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
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// Floating point constants for Quad, Double, Single, and Half precisions
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`define Q_LEN 32'd128
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`define Q_NE 32'd15
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`define Q_NF 32'd112
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`define Q_BIAS 32'd16383
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`define Q_FMT 2'd3
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`define D_LEN 32'd64
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`define D_NE 32'd11
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`define D_NF 32'd52
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`define D_BIAS 32'd1023
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`define D_FMT 2'd1
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`define S_LEN 32'd32
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`define S_NE 32'd8
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`define S_NF 32'd23
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`define S_BIAS 32'd127
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`define S_FMT 2'd0
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`define H_LEN 32'd16
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`define H_NE 32'd5
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`define H_NF 32'd10
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`define H_BIAS 32'd15
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`define H_FMT 2'd2
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// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
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`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN)
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`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE)
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`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF)
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`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0)
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`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS)
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/* Delete once tested dh 10/10/22
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`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN)
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`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE)
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`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF)
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`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2)
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`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)*/
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// Floating point constants needed for FPU paramerterization
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`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED))
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`define FMTBITS ((32)'(`FPSIZES>=3)+1)
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`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN)
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`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE)
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`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF)
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`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2)
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`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS)
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`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN)
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`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE)
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`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF)
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`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2)
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`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS)
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// largest length in IEU/FPU
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`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF))
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`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN))
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`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1))
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`define NORMSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6)))
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`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ))
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`define CORRSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4)))
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// division constants
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`define DIVN (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input
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`define LOGR ($clog2(`RADIX)) // r = log(R)
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`define RK (`LOGR*`DIVCOPIES) // r*k used for intdiv preproc
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`define LOGRK ($clog2(`RK)) // log2(r*k)
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`define FPDUR ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4))
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`define DURLEN ($clog2(`FPDUR+1))
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`define DIVb (`FPDUR*`LOGR*`DIVCOPIES-1) // canonical fdiv size (b)
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`define DIVBLEN ($clog2(`DIVb+1)-1)
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`define DIVa (`DIVb+1-`XLEN) // used for idiv on fpu
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// Disable spurious Verilator warnings
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/* verilator lint_off STMTDLY */
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/* verilator lint_off ASSIGNDLY */
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/* verilator lint_off PINCONNECTEMPTY */
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@ -23,19 +23,120 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// constants defining different privilege modes
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// defined in Table 1.1 of the privileged spec
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`define M_MODE (2'b11)
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`define S_MODE (2'b01)
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`define U_MODE (2'b00)
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// Virtual Memory Constants
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`define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9)
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`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS))
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`define PPN_BITS (`XLEN==32 ? 22 : 44)
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`define PA_BITS (`XLEN==32 ? 34 : 56)
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`define SVMODE_BITS (`XLEN==32 ? 1 : 4)
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`define ASID_BASE (`XLEN==32 ? 22 : 44)
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`define ASID_BITS (`XLEN==32 ? 9 : 16)
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// constants to check SATP_MODE against
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// defined in Table 4.3 of the privileged spec
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`define NO_TRANSLATE 0
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`define SV32 1
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`define SV39 8
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`define SV48 9
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// macros to define supported modes
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`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
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`define B_SUPPORTED ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)) // not based on MISA
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`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
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`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
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`define E_SUPPORTED ((`MISA >> 4) % 2 == 1)
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`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
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`define I_SUPPORTED ((`MISA >> 8) % 2 == 1)
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`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
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`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1)
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`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
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`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
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// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
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// logarithm of XLEN, used for number of index bits to select
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`define LOG_XLEN (`XLEN == 32 ? 5 : 6)
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// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
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`define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
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// Floating point constants for Quad, Double, Single, and Half precisions
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`define Q_LEN 32'd128
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`define Q_NE 32'd15
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`define Q_NF 32'd112
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`define Q_BIAS 32'd16383
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`define Q_FMT 2'd3
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`define D_LEN 32'd64
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`define D_NE 32'd11
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`define D_NF 32'd52
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`define D_BIAS 32'd1023
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`define D_FMT 2'd1
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`define S_LEN 32'd32
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`define S_NE 32'd8
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`define S_NF 32'd23
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`define S_BIAS 32'd127
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`define S_FMT 2'd0
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`define H_LEN 32'd16
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`define H_NE 32'd5
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`define H_NF 32'd10
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`define H_BIAS 32'd15
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`define H_FMT 2'd2
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// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
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`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN)
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`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE)
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`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF)
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`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0)
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`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS)
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/* Delete once tested dh 10/10/22
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`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN)
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`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE)
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`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF)
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`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2)
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`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)*/
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// Floating point constants needed for FPU paramerterization
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`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED))
|
||||
`define FMTBITS ((32)'(`FPSIZES>=3)+1)
|
||||
`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN)
|
||||
`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE)
|
||||
`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF)
|
||||
`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2)
|
||||
`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS)
|
||||
`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN)
|
||||
`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE)
|
||||
`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF)
|
||||
`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2)
|
||||
`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS)
|
||||
|
||||
// largest length in IEU/FPU
|
||||
`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF))
|
||||
`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN))
|
||||
`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1))
|
||||
`define NORMSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6)))
|
||||
`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ))
|
||||
`define CORRSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4)))
|
||||
|
||||
// division constants
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// eventually move to each config
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
`define DIVN (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input
|
||||
`define LOGR ($clog2(`RADIX)) // r = log(R)
|
||||
`define RK (`LOGR*`DIVCOPIES) // r*k used for intdiv preproc
|
||||
`define LOGRK ($clog2(`RK)) // log2(r*k)
|
||||
`define FPDUR ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4))
|
||||
`define DURLEN ($clog2(`FPDUR+1))
|
||||
`define DIVb (`FPDUR*`LOGR*`DIVCOPIES-1) // canonical fdiv size (b)
|
||||
`define DIVBLEN ($clog2(`DIVb+1)-1)
|
||||
`define DIVa (`DIVb+1-`XLEN) // used for idiv on fpu
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
|
||||
// shared constants
|
||||
`include "wally-constants.vh"
|
||||
// Disable spurious Verilator warnings
|
||||
|
||||
/* verilator lint_off STMTDLY */
|
||||
/* verilator lint_off ASSIGNDLY */
|
||||
/* verilator lint_off PINCONNECTEMPTY */
|
||||
|
|
|
|||
|
|
@ -543,7 +543,7 @@ module riscvassertions;
|
|||
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
|
||||
assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF");
|
||||
assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
|
||||
assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
|
||||
assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported");
|
||||
assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
|
||||
assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
|
||||
assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue