mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-19 11:34:50 -04:00
Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates
This commit is contained in:
Jordan Carlin
commit
e98330bcdf
26 changed files with 195 additions and 757 deletions
299
.gitignore
vendored
299
.gitignore
vendored
|
|
@ -1,78 +1,46 @@
|
|||
# General file extensions to ignore
|
||||
.nfs*
|
||||
*.objdump*
|
||||
*.o
|
||||
*.d
|
||||
*.a
|
||||
*.vstf
|
||||
*.vcd
|
||||
*.signature.output
|
||||
*.dtb
|
||||
*.log
|
||||
*.map
|
||||
*.elf*
|
||||
*.list
|
||||
|
||||
# General directories to ignore
|
||||
.vscode/
|
||||
__pycache__/
|
||||
**/work*
|
||||
**/wally_*.log
|
||||
/**/obj_dir*
|
||||
/**/gmon*
|
||||
|
||||
.nfs*
|
||||
|
||||
__pycache__/
|
||||
.vscode/
|
||||
|
||||
#External repos
|
||||
addins/riscv-arch-test/Makefile.include
|
||||
addins/riscv-tests/target
|
||||
addins/TestFloat-3e/build/Linux-x86_64-GCC/*
|
||||
|
||||
|
||||
#vsim work files to ignore
|
||||
transcript
|
||||
vsim.wlf
|
||||
wlft*
|
||||
wlft*
|
||||
/imperas-riscv-tests/FunctionRadix_32.addr
|
||||
/imperas-riscv-tests/FunctionRadix_64.addr
|
||||
/imperas-riscv-tests/FunctionRadix.addr
|
||||
/imperas-riscv-tests/ProgramMap.txt
|
||||
/imperas-riscv-tests/logs
|
||||
*.o
|
||||
*.d
|
||||
*.vstf
|
||||
testsBP/*/*/*.elf*
|
||||
testsBP/*/OBJ/*
|
||||
testsBP/*/*.a
|
||||
tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/*
|
||||
tests/riscof/riscof_work/
|
||||
# Tests
|
||||
tests/riscof/config32.ini
|
||||
tests/riscof/config32e.ini
|
||||
tests/riscof/config64.ini
|
||||
tests/linux-testgen/linux-testvectors/*
|
||||
!tests/linux-testgen/linux-testvectors/tvCopier.py
|
||||
!tests/linux-testgen/linux-testvectors/tvLinker.sh
|
||||
!tests/linux-testgen/linux-testvectors/tvUnlinker.sh
|
||||
tests/linux-testgen/buildroot
|
||||
tests/linux-testgen/buildroot-image-output
|
||||
tests/linux-testgen/buildroot-config-src/main.config.old
|
||||
tests/linux-testgen/buildroot-config-src/linux.config.old
|
||||
tests/linux-testgen/buildroot-config-src/busybox.config.old
|
||||
tests/riscof/riscof_work/
|
||||
tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/**
|
||||
tests/fp/vectors/*.tv
|
||||
tests/fp/combined_IF_vectors/IF_vectors/*.tv
|
||||
tests/custom/*/*/
|
||||
tests/custom/*/*/*.memfile
|
||||
tests/riscvdv
|
||||
tests/functcov
|
||||
|
||||
# Linux
|
||||
linux/buildroot
|
||||
linux/testvector-generation/boottrace.S
|
||||
linux/testvector-generation/boottrace_disasm.log
|
||||
sim/slack-notifier/slack-webhook-url.txt
|
||||
fpga/generator/IP
|
||||
fpga/generator/vivado.*
|
||||
fpga/generator/.Xil/*
|
||||
fpga/generator/WallyFPGA*
|
||||
fpga/generator/reports/
|
||||
fpga/generator/*.log
|
||||
fpga/generator/*.jou
|
||||
*.objdump*
|
||||
*.signature.output
|
||||
examples/asm/sumtest/sumtest
|
||||
examples/asm/example/example
|
||||
examples/C/sum/sum
|
||||
examples/C/fir/fir
|
||||
examples/fp/softfloat_demo/softfloat_demo
|
||||
examples/fp/softfloat_demo/softfloat_demoDP
|
||||
examples/fp/softfloat_demo/softfloat_demoQP
|
||||
examples/fp/softfloat_demo/softfloat_demoSP
|
||||
examples/fp/fpcalc/fpcalc
|
||||
examples/fp/sqrttest/sqrttest
|
||||
examples/C/inline/inline
|
||||
examples/C/mcmodel/mcmodel
|
||||
examples/C/sum_mixed/sum_mixed
|
||||
examples/asm/trap/trap
|
||||
examples/asm/etc/pause
|
||||
src/fma/fma16_testgen
|
||||
linux/devicetree/debug/*
|
||||
!linux/devicetree/debug/dump-dts.sh
|
||||
linux/testvector-generation/genCheckpoint.gdb
|
||||
|
|
@ -80,10 +48,30 @@ linux/testvector-generation/silencePipe
|
|||
linux/testvector-generation/silencePipe.control
|
||||
linux/testvector-generation/fixBinMem
|
||||
linux/testvector-generation/qemu-serial
|
||||
*.dtb
|
||||
|
||||
# FPGA
|
||||
fpga/generator/IP
|
||||
fpga/generator/vivado.*
|
||||
fpga/generator/.Xil/*
|
||||
fpga/generator/WallyFPGA*
|
||||
fpga/generator/reports/
|
||||
fpga/generator/*.jou
|
||||
fpga/src/sdc/*
|
||||
fpga/src/sdc.tar.gz
|
||||
fpga/src/CopiedFiles_do_not_add_to_repo/*
|
||||
fpga/generator/sim/imp-funcsim.v
|
||||
fpga/generator/sim/imp-timesim.sdf
|
||||
fpga/generator/sim/imp-timesim.v
|
||||
fpga/generator/sim/syn-funcsim.v
|
||||
fpga/rvvidaemon/rvvidaemon
|
||||
fpga/zsbl/OBJ/*
|
||||
fpga/zsbl/bin/*
|
||||
fpga/src/boot.mem
|
||||
fpga/src/data.mem
|
||||
|
||||
# Synthesis
|
||||
synthDC/WORK
|
||||
synthDC/alib-52
|
||||
synthDC/*.log
|
||||
synthDC/*.svf
|
||||
synthDC/runs/
|
||||
synthDC/newRuns
|
||||
|
|
@ -92,126 +80,52 @@ synthDC/ppa/plots
|
|||
synthDC/wallyplots/
|
||||
synthDC/runArchive
|
||||
synthDC/hdl
|
||||
sim/power.saif
|
||||
tests/fp/vectors
|
||||
synthDC/Summary.csv
|
||||
tests/custom/work
|
||||
tests/custom/*/*/*.list
|
||||
tests/custom/*/*/*.elf
|
||||
tests/custom/*/*/*.map
|
||||
tests/custom/*/*/*.memfile
|
||||
tests/custom/crt0/*.a
|
||||
tests/custom/*/*.elf*
|
||||
sim/sd_model.log
|
||||
fpga/src/sdc/*
|
||||
fpga/src/sdc.tar.gz
|
||||
fpga/src/CopiedFiles_do_not_add_to_repo/*
|
||||
sim/branch.log
|
||||
/fpga/generator/sim/imp-funcsim.v
|
||||
/fpga/generator/sim/imp-timesim.sdf
|
||||
/fpga/generator/sim/imp-timesim.v
|
||||
/fpga/generator/sim/syn-funcsim.v
|
||||
external
|
||||
sim/results
|
||||
tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S
|
||||
tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag
|
||||
sim/branch_BP_GSHARE10.log
|
||||
sim/branch_BP_GSHARE16.log
|
||||
sim/questa/imperas.log
|
||||
sim/results-error/
|
||||
sim/test1.rep
|
||||
sim/questa/vsim.log
|
||||
tests/coverage/*.elf
|
||||
*.elf.memfile
|
||||
sim/*/*Cache.log
|
||||
sim/branch
|
||||
tests/fp/combined_IF_vectors/IF_vectors/*.tv
|
||||
/sim/branch-march14.tar.gz
|
||||
/sim/gshareforward-no-class
|
||||
/sim/lint-wally_32
|
||||
/sim/lint-wally_32e
|
||||
/sim/local16.txt
|
||||
/sim/localhistory_m6k10_results_april24.txt
|
||||
/sim/log.log
|
||||
/sim/obj_dir/Vtestbench.cpp
|
||||
/sim/obj_dir/Vtestbench.h
|
||||
/sim/obj_dir/Vtestbench.mk
|
||||
/sim/obj_dir/Vtestbench__ConstPool_0.cpp
|
||||
/sim/obj_dir/Vtestbench__Syms.cpp
|
||||
/sim/obj_dir/Vtestbench__Syms.h
|
||||
/sim/obj_dir/Vtestbench___024root.h
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__10.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__11.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__6.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__7.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__8.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__9.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024unit.h
|
||||
/sim/obj_dir/Vtestbench___024unit__DepSet_hf87c9ffd__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024unit__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench__verFiles.dat
|
||||
/sim/obj_dir/Vtestbench_classes.mk
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9.h
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__1.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20.h
|
||||
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_h3df7cb71__0.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__Slow.cpp
|
||||
sim/bp-results/*.log
|
||||
sim/branch*.log
|
||||
/tests/custom/fpga-test-sdc/bin/fpga-test-sdc
|
||||
|
||||
# Benchmarks
|
||||
benchmarks/embench/wally*.json
|
||||
benchmarks/embench/run*
|
||||
sim/cfi.log
|
||||
benchmarks/coremark/coremark_results.csv
|
||||
|
||||
# Simulation
|
||||
sim/*.svg
|
||||
sim/power.saif
|
||||
sim/results
|
||||
sim/results-error/
|
||||
sim/test1.rep
|
||||
sim/branch
|
||||
sim/branch-march14.tar.gz
|
||||
sim/gshareforward-no-class
|
||||
sim/local16.txt
|
||||
sim/localhistory_m6k10_results_april24.txt
|
||||
sim/cfi/*
|
||||
sim/branch/*
|
||||
sim/obj_dir
|
||||
examples/verilog/fulladder/obj_dir
|
||||
examples/verilog/fulladder/fulladder.vcd
|
||||
config/deriv
|
||||
docs/docker/buildroot-config-src
|
||||
docs/docker/testvector-generation
|
||||
sim/questa/cov
|
||||
sim/questa/fcovrvvi
|
||||
sim/questa/fcovrvvi_logs
|
||||
sim/questa/fcovrvvi_ucdb
|
||||
sim/covhtmlreport/
|
||||
sim/*/*Cache.log
|
||||
|
||||
# Questa
|
||||
sim/questa/logs
|
||||
sim/questa/wkdir
|
||||
sim/questa/ucdb
|
||||
sim/questa/fcov
|
||||
sim/questa/cov
|
||||
sim/questa/fcov
|
||||
sim/questa/fcovrvvi
|
||||
sim/questa/fcovrvvi_logs
|
||||
sim/questa/fcovrvvi_ucdb
|
||||
sim/questa/fcov_logs
|
||||
sim/questa/fcov_ucdb
|
||||
sim/verilator/logs
|
||||
sim/verilator/wkdir
|
||||
sim/questa/functcov_logs
|
||||
sim/questa/functcov_ucdbs
|
||||
sim/questa/functcov
|
||||
sim/questa/riscv.ucdb
|
||||
transcript
|
||||
vsim.wlf
|
||||
wlft*
|
||||
|
||||
# VCS
|
||||
sim/vcs/logs
|
||||
sim/vcs/wkdir
|
||||
sim/vcs/ucdb
|
||||
benchmarks/coremark/coremark_results.csv
|
||||
fpga/zsbl/OBJ/*
|
||||
fpga/zsbl/bin/*
|
||||
sim/*.svg
|
||||
sim/vcs/csrc
|
||||
sim/vcs/profileReport*
|
||||
sim/vcs/program.out
|
||||
|
|
@ -220,17 +134,13 @@ sim/vcs/simprofile_dir
|
|||
sim/vcs/ucli.key
|
||||
sim/vcs/verdi_config_file
|
||||
sim/vcs/vcdplus.vpd
|
||||
sim/*/testbench.vcd
|
||||
sim/questa/imperas.log
|
||||
sim/questa/functcov.log
|
||||
sim/questa/functcov_logs/*
|
||||
sim/questa/functcov_ucdbs/*
|
||||
sim/questa/functcov
|
||||
sim/questa/riscv.ucdb
|
||||
sim/questa/riscv.ucdb.log
|
||||
sim/questa/riscv.ucdb.summary.log
|
||||
sim/questa/riscv.ucdb.testdetails.log
|
||||
tests/riscvdv
|
||||
sim/vcs/simprofile*
|
||||
|
||||
# Verilator
|
||||
sim/verilator/logs
|
||||
sim/verilator/wkdir
|
||||
|
||||
# Examples
|
||||
examples/verilog/fulladder/csrc/
|
||||
examples/verilog/fulladder/profileReport.html
|
||||
examples/verilog/fulladder/profileReport.json
|
||||
|
|
@ -240,10 +150,27 @@ examples/verilog/fulladder/simprofile_dir/
|
|||
examples/verilog/fulladder/simv.daidir/
|
||||
examples/verilog/fulladder/ucli.key
|
||||
examples/verilog/fulladder/verdi_config_file
|
||||
examples/fp/softfloat_demo/softfloat_demo
|
||||
examples/fp/softfloat_demo/softfloat_demoDP
|
||||
examples/fp/softfloat_demo/softfloat_demoQP
|
||||
examples/fp/softfloat_demo/softfloat_demoSP
|
||||
examples/fp/fpcalc/fpcalc
|
||||
examples/fp/sqrttest/sqrttest
|
||||
examples/crypto/gfmul/gfmul
|
||||
tests/functcov
|
||||
tests/functcov/*
|
||||
tests/functcov/*/*
|
||||
sim/vcs/simprofile*
|
||||
sim/verilator/verilator.log
|
||||
/fpga/rvvidaemon/rvvidaemon
|
||||
examples/C/fir/fir
|
||||
examples/C/inline/inline
|
||||
examples/C/mcmodel/mcmodel_medany
|
||||
examples/C/mcmodel/mcmodel_medlow
|
||||
examples/C/sum/sum
|
||||
examples/C/sum_mixed/sum_mixed
|
||||
examples/asm/sumtest/sumtest
|
||||
examples/asm/example/example
|
||||
examples/asm/trap/trap
|
||||
examples/asm/etc/pause
|
||||
|
||||
# Other
|
||||
external
|
||||
config/deriv
|
||||
sim/slack-notifier/slack-webhook-url.txt
|
||||
docs/docker/buildroot-config-src
|
||||
docs/docker/testvector-generation
|
||||
|
|
|
|||
6
Makefile
6
Makefile
|
|
@ -5,7 +5,8 @@
|
|||
SIM = ${WALLY}/sim
|
||||
|
||||
all:
|
||||
make riscof
|
||||
make riscof
|
||||
make zsbl
|
||||
make testfloat
|
||||
# make verify
|
||||
make coverage
|
||||
|
|
@ -20,6 +21,9 @@ testfloat:
|
|||
cd ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC; make
|
||||
cd ${WALLY}/tests/fp; ./create_all_vectors.sh
|
||||
|
||||
zsbl:
|
||||
$(MAKE) -C ${WALLY}/fpga/zsbl
|
||||
|
||||
verify:
|
||||
cd ${SIM}; ./regression-wally
|
||||
cd ${SIM}/sim; ./sim-testfloat-batch all
|
||||
|
|
|
|||
|
|
@ -1,43 +1,42 @@
|
|||
dst := IP
|
||||
|
||||
# vcu118
|
||||
# export XILINX_PART := xcvu9p-flga2104-2L-e
|
||||
# export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
|
||||
# export board := vcu118
|
||||
all: ArtyA7
|
||||
|
||||
# vcu108
|
||||
# export XILINX_PART := xcvu095-ffva2104-2-e
|
||||
# export XILINX_BOARD := xilinx.com:vcu108:part0:1.7
|
||||
# export board := vcu108
|
||||
.PHONY: ArtyA7 vcu118 vcu108
|
||||
|
||||
# Arty A7
|
||||
export XILINX_PART := xc7a100tcsg324-1
|
||||
export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
|
||||
export board := ArtyA7
|
||||
ArtyA7: export XILINX_PART := xc7a100tcsg324-1
|
||||
ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
|
||||
ArtyA7: export board := ArtyA7
|
||||
ArtyA7: FPGA_Arty
|
||||
|
||||
# for Arty A7 and S7 boards
|
||||
all: FPGA_Arty
|
||||
vcu118: export XILINX_PART := xcvu9p-flga2104-2L-e
|
||||
vcu118: export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
|
||||
vcu118: export board := vcu118
|
||||
vcu118: FPGA_VCU
|
||||
|
||||
# VCU 108 and VCU 118 boards
|
||||
#all: FPGA_VCU
|
||||
vcu108: export XILINX_PART := xcvu095-ffva2104-2-e
|
||||
vcu108: export XILINX_BOARD := xilinx.com:vcu108:part0:1.7
|
||||
vcu108: export board := vcu108
|
||||
vcu108: FPGA_VCU
|
||||
|
||||
.PHONY: FPGA_Arty FPGA_VCU
|
||||
FPGA_Arty: PreProcessFiles IP_Arty
|
||||
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
|
||||
|
||||
FPGA_VCU: PreProcessFiles IP_VCU
|
||||
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
|
||||
|
||||
# Generate IP Blocks
|
||||
.PHONY: IP_Arty IP_VCU
|
||||
IP_VCU: $(dst)/xlnx_proc_sys_reset.log \
|
||||
$(dst)/xlnx_ddr4-$(board).log \
|
||||
MEM_VCU \
|
||||
$(dst)/xlnx_axi_clock_converter.log \
|
||||
$(dst)/xlnx_ahblite_axi_bridge.log \
|
||||
$(dst)/xlnx_axi_crossbar.log \
|
||||
$(dst)/xlnx_axi_dwidth_conv_32to64.log \
|
||||
$(dst)/xlnx_axi_dwidth_conv_64to32.log \
|
||||
$(dst)/xlnx_axi_prtcl_conv.log
|
||||
|
||||
IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
|
||||
$(dst)/xlnx_ddr3-$(board).log \
|
||||
MEM_Arty \
|
||||
$(dst)/xlnx_mmcm.log \
|
||||
$(dst)/xlnx_axi_clock_converter.log \
|
||||
$(dst)/xlnx_ahblite_axi_bridge.log
|
||||
|
|
@ -46,7 +45,15 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
|
|||
#$(dst)/xlnx_axi_dwidth_conv_64to32.log \
|
||||
#$(dst)/xlnx_axi_prtcl_conv.log
|
||||
|
||||
# Generate Memory IP Blocks
|
||||
.PHONY: MEM_VCU MEM_Arty
|
||||
MEM_VCU:
|
||||
$(MAKE) $(dst)/xlnx_ddr4-$(board).log
|
||||
MEM_Arty:
|
||||
$(MAKE) $(dst)/xlnx_ddr3-$(board).log
|
||||
|
||||
# Copy files and make necessary modifications
|
||||
.PHONY: PreProcessFiles
|
||||
PreProcessFiles:
|
||||
$(MAKE) -C ../../sim deriv
|
||||
rm -rf ../src/CopiedFiles_do_not_add_to_repo/
|
||||
|
|
@ -63,18 +70,24 @@ PreProcessFiles:
|
|||
sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
|
||||
sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv
|
||||
|
||||
# Generate Individual IP Blocks
|
||||
$(dst)/%.log: %.tcl
|
||||
mkdir -p IP
|
||||
cd IP;\
|
||||
vivado -mode batch -source ../$*.tcl | tee $*.log
|
||||
|
||||
# Clean
|
||||
.PHONY: cleanIP cleanLogs cleanFPGA cleanAll
|
||||
cleanIP:
|
||||
rm -rf IP
|
||||
|
||||
cleanLogs:
|
||||
rm -rf *.jou *.log
|
||||
|
||||
cleanFPGA:
|
||||
rm -rf WallyFPGA.* reports sim .Xil
|
||||
|
||||
cleanAll: cleanIP cleanLogs cleanFPGA
|
||||
|
||||
# Aliases
|
||||
.PHONY: arty artya7 VCU118 VCU108
|
||||
arty artya7: ArtyA7
|
||||
VCU118: vcu118
|
||||
VCU108: vcu108
|
||||
|
|
|
|||
|
|
@ -1,513 +0,0 @@
|
|||
8001819300002197
|
||||
4281420141014081
|
||||
4481440143814301
|
||||
4681460145814501
|
||||
4881480147814701
|
||||
4a814a0149814901
|
||||
4c814c014b814b01
|
||||
4e814e014d814d01
|
||||
0110011b4f814f01
|
||||
059b45011161016e
|
||||
0004063705fe0010
|
||||
1f6000ef8006061b
|
||||
0ff003930000100f
|
||||
4e952e3110060e37
|
||||
c602829b0053f2b7
|
||||
2023fe02dfe312fd
|
||||
829b0053f2b7007e
|
||||
fe02dfe312fdc602
|
||||
4de31efd000e2023
|
||||
059bf1402573fdd0
|
||||
0000061705e20870
|
||||
0010029b01260613
|
||||
68110002806702fe
|
||||
0085179bf0080813
|
||||
038008130107f7b3
|
||||
480508a86c632781
|
||||
1533357902a87963
|
||||
38030000181700a8
|
||||
1c6301057833f268
|
||||
081a403018370808
|
||||
0105783342280813
|
||||
1815751308081063
|
||||
00367513c295e14d
|
||||
654ded510207e793
|
||||
c1701ff00613f130
|
||||
0637c530fff6861b
|
||||
664dcd10167d0200
|
||||
17fd001007b7c25c
|
||||
859b5a5cc20cd21c
|
||||
02062a23dfed0007
|
||||
4785fffd561c664d
|
||||
4501461c06f59063
|
||||
4a1cc35c465cc31c
|
||||
e29dc75c4a5cc71c
|
||||
0c63086008138082
|
||||
1ae30a9008130105
|
||||
b7710017e793f905
|
||||
e793b75901d7e793
|
||||
5f5c674db7410197
|
||||
66cd02072e23dffd
|
||||
fff78513ff7d5698
|
||||
40a0053300a03533
|
||||
bfb100a7e7938082
|
||||
e0a2715d8082557d
|
||||
e486f052f44ef84a
|
||||
fa13e85aec56fc26
|
||||
843289ae892a0086
|
||||
00959993000a1463
|
||||
864ac4396b054a85
|
||||
0009859b4549870a
|
||||
0004049b05540363
|
||||
86a66485008b7363
|
||||
870a87aaec7ff0ef
|
||||
4531458146014681
|
||||
f0ef0207c9639c05
|
||||
17820094979beb1f
|
||||
873e020541639381
|
||||
993e99ba020a1963
|
||||
870aa8094501f85d
|
||||
e8bff0ef45454685
|
||||
60a64505fe0559e3
|
||||
79a2794274e26406
|
||||
61616b426ae27a02
|
||||
9301020497138082
|
||||
f40647057179b7f1
|
||||
d79867cdec26f022
|
||||
dff58b85571c674d
|
||||
2423d35c03600793
|
||||
fffd571c674d0207
|
||||
0007a737b00026f3
|
||||
b00027f311f70713
|
||||
674dfef77de38f95
|
||||
4f5ccf9d8b895b1c
|
||||
26f3cf5c0027e793
|
||||
071305f5e737b000
|
||||
8f95b00027f30ff7
|
||||
4f5c674dfef77de3
|
||||
b00026f3cf5c9bf5
|
||||
67f7071300989737
|
||||
7de38f95b00027f3
|
||||
458146014681fef7
|
||||
ddbff0ef4501870a
|
||||
059346014681870a
|
||||
dcbff0ef45211aa0
|
||||
1aa007134782e939
|
||||
816393d117d24411
|
||||
85220ff0041302e7
|
||||
614564e270a27402
|
||||
46e3da5ff0efa0cd
|
||||
0207c7634782fe05
|
||||
458146014681870a
|
||||
d8bff0ef03700513
|
||||
46014681870a87aa
|
||||
0a900513403005b7
|
||||
4409bf7dfc07d9e3
|
||||
c3998b8583f9bfe1
|
||||
4681870a00846413
|
||||
f0ef450945814601
|
||||
870afa0540e3d59f
|
||||
123405b746014681
|
||||
46e3d45ff0ef450d
|
||||
870a77c14482f805
|
||||
85a6460146818cfd
|
||||
4ae3d2dff0ef451d
|
||||
d3d8470567cdf605
|
||||
000f4737b00026f3
|
||||
b00027f323f70713
|
||||
67cdfef77de38f95
|
||||
4681870a0007ae23
|
||||
0370051385a64601
|
||||
f2054fe3cf7ff0ef
|
||||
458146014681870a
|
||||
ce3ff0ef08600513
|
||||
4681870af20545e3
|
||||
4541200005934601
|
||||
f0055de3ccfff0ef
|
||||
3023bf010113bf09
|
||||
4605842a86aa4081
|
||||
40113423850a4585
|
||||
86a265a6da5ff0ef
|
||||
d99ff0ef04084605
|
||||
2201358322813603
|
||||
86a2260508700513
|
||||
d81ff0ef05629e0d
|
||||
2a0135832a813603
|
||||
9e0d86a226054505
|
||||
3603d6bff0ef057e
|
||||
0513320135833281
|
||||
9e0d86a226054010
|
||||
3083d53ff0ef0556
|
||||
4501400134034081
|
||||
0000808241010113
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
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|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
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|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
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|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
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|
||||
0000000000000000
|
||||
0000000000000000
|
||||
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|
||||
0000000000000000
|
||||
0000000000000000
|
||||
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|
||||
0000000000000000
|
||||
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|
||||
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|
||||
0000000000000000
|
||||
0000000000000000
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
0000000000000000
|
||||
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|
||||
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|
||||
0000000000000000
|
||||
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|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
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|
||||
0000000000000000
|
||||
0000000000000000
|
||||
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|
||||
0000000000000000
|
||||
0000000000000000
|
||||
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|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
00600100d2e3ca40
|
||||
|
|
@ -24,7 +24,7 @@ LIBRARY_FILES :=
|
|||
|
||||
MARCH :=-march=rv64imfdc_zifencei
|
||||
MABI :=-mabi=lp64d
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib
|
||||
LINKER :=linker1000.x
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv",
|
|||
"elf64-littleriscv")
|
||||
OUTPUT_ARCH(riscv)
|
||||
ENTRY(_start)
|
||||
SEARCH_DIR("/opt/riscv/riscv64-unknown-elf/lib");
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
# imperas.ic
|
||||
# Initialization file for ImperasDV lock step simulation
|
||||
# David_Harris@hmc.edu 15 August 2024
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#--mpdconsole
|
||||
#--gdbconsole
|
||||
#--showoverrides
|
||||
|
|
@ -68,6 +73,9 @@
|
|||
--override cpu/PMP_registers=16
|
||||
--override cpu/PMP_undefined=T
|
||||
|
||||
# mstatus.FS is set dirty on any write to a FPR, or when a fp operation signals an exception
|
||||
--override cpu/mstatus_fs_mode=rvfs_write_nz
|
||||
|
||||
# PMA Settings
|
||||
# 'r': read access allowed
|
||||
# 'w': write access allowed
|
||||
|
|
@ -101,7 +109,7 @@
|
|||
|
||||
# Add Imperas simulator application instruction tracing
|
||||
# uncomment these to provide tracing
|
||||
#--verbose --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange # --traceafter 300000000
|
||||
--verbose --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange # --traceafter 300000000
|
||||
--override cpu/debugflags=6 --override cpu/verbose=1
|
||||
--override cpu/show_c_prefix=T
|
||||
|
||||
|
|
|
|||
|
|
@ -148,9 +148,12 @@ module decompress import cvw::*; #(parameter cvw_t P) (
|
|||
5'b01101: LInstrD = {1'b1, immCJ, 5'b00000, 7'b1101111}; // c.j
|
||||
5'b01110: LInstrD = {1'b1, immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
|
||||
5'b01111: LInstrD = {1'b1, immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
|
||||
5'b10000: if (rds1 != 5'b0) begin
|
||||
if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli; shamt[5] must be 0 in RV32C
|
||||
end else if (immSH != 0) LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.slli with rd = 0, immm != 0 is a HINT, treated as nop
|
||||
5'b10000: if (immSH != 0) begin
|
||||
if (P.XLEN > 32 | ~immSH[5]) begin // shamt[5] = 1 is reserved in RV32C
|
||||
if (rds1 != 5'b0) LInstrD = {1'b1, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
|
||||
else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.slli with rd = 0 is a HINT, treated as nop
|
||||
end
|
||||
end else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.slli with immm = 0 is a HINT, treated as nop
|
||||
5'b10001: if (P.ZCD_SUPPORTED) LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
|
||||
5'b10010: if (rds1 != 5'b0) LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
|
||||
5'b10011: if (P.XLEN == 32) begin
|
||||
|
|
|
|||
|
|
@ -110,7 +110,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
|
|||
logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
|
||||
logic CSRMWriteM, CSRSWriteM, CSRUWriteM;
|
||||
logic UngatedCSRMWriteM;
|
||||
logic WriteFRMM, WriteFFLAGSM;
|
||||
logic WriteFRMM, SetOrWriteFFLAGSM;
|
||||
logic [P.XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextMtvalM;
|
||||
logic [4:0] NextCauseM;
|
||||
logic [11:0] CSRAdrM;
|
||||
|
|
@ -222,7 +222,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
|
|||
csrsr #(P) csrsr(.clk, .reset, .StallW,
|
||||
.WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM,
|
||||
.TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
|
||||
.mretM, .sretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM, .SelHPTW,
|
||||
.mretM, .sretM, .WriteFRMM, .SetOrWriteFFLAGSM, .CSRWriteValM, .SelHPTW,
|
||||
.MSTATUS_REGW, .SSTATUS_REGW, .MSTATUSH_REGW,
|
||||
.STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
|
||||
.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
|
||||
|
|
@ -267,14 +267,14 @@ module csr import cvw::*; #(parameter cvw_t P) (
|
|||
if (P.F_SUPPORTED) begin:csru
|
||||
csru #(P) csru(.clk, .reset, .InstrValidNotFlushedM,
|
||||
.CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,
|
||||
.SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
|
||||
.SetFflagsM, .FRM_REGW, .WriteFRMM, .SetOrWriteFFLAGSM,
|
||||
.IllegalCSRUAccessM);
|
||||
end else begin
|
||||
assign FRM_REGW = '0;
|
||||
assign CSRUReadValM = '0;
|
||||
assign IllegalCSRUAccessM = 1'b1;
|
||||
assign WriteFRMM = 1'b0;
|
||||
assign WriteFFLAGSM = 1'b0;
|
||||
assign SetOrWriteFFLAGSM = 1'b0;
|
||||
end
|
||||
|
||||
if (P.ZICNTR_SUPPORTED) begin:counters
|
||||
|
|
|
|||
|
|
@ -159,11 +159,11 @@ module csrc import cvw::*; #(parameter cvw_t P) (
|
|||
if (P.XLEN==64) begin // 64-bit counter reads
|
||||
// Veri lator doesn't realize this only occurs for XLEN=64
|
||||
/* verilator lint_off WIDTH */
|
||||
if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT
|
||||
if (CSRAdrM == TIME & ~CSRWriteM) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT
|
||||
/* verilator lint_on WIDTH */
|
||||
else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME)
|
||||
CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS)
|
||||
else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS & ~CSRWriteM) // read-only
|
||||
CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else begin
|
||||
CSRCReadValM = '0;
|
||||
|
|
@ -172,16 +172,16 @@ module csrc import cvw::*; #(parameter cvw_t P) (
|
|||
end else begin // 32-bit counter reads
|
||||
// Veril ator doesn't realize this only occurs for XLEN=32
|
||||
/* verilator lint_off WIDTH */
|
||||
if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
|
||||
else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32];
|
||||
if (CSRAdrM == TIME & ~CSRWriteM) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
|
||||
else if (CSRAdrM == TIMEH & ~CSRWriteM) CSRCReadValM = MTIME_CLINT[63:32];
|
||||
/* verilator lint_on WIDTH */
|
||||
else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME)
|
||||
CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS)
|
||||
else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS & ~CSRWriteM) // read-only
|
||||
CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+P.COUNTERS & CSRAdrM != MTIMEH)
|
||||
CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+P.COUNTERS)
|
||||
else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+P.COUNTERS & ~CSRWriteM) // read-only
|
||||
CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
|
||||
else begin
|
||||
CSRCReadValM = '0;
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ module csrsr import cvw::*; #(parameter cvw_t P) (
|
|||
input logic TrapM, FRegWriteM,
|
||||
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
|
||||
input logic mretM, sretM,
|
||||
input logic WriteFRMM, WriteFFLAGSM,
|
||||
input logic WriteFRMM, SetOrWriteFFLAGSM,
|
||||
input logic [P.XLEN-1:0] CSRWriteValM,
|
||||
input logic SelHPTW,
|
||||
output logic [P.XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW,
|
||||
|
|
@ -209,6 +209,6 @@ module csrsr import cvw::*; #(parameter cvw_t P) (
|
|||
STATUS_SPIE <= P.S_SUPPORTED & CSRWriteValM[5];
|
||||
STATUS_SIE <= P.S_SUPPORTED & CSRWriteValM[1];
|
||||
STATUS_UBE <= CSRWriteValM[6] & P.U_SUPPORTED & P.BIGENDIAN_SUPPORTED;
|
||||
end else if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= 2'b11;
|
||||
end else if (FRegWriteM | WriteFRMM | SetOrWriteFFLAGSM) STATUS_FS_INT <= 2'b11;
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ module csru import cvw::*; #(parameter cvw_t P) (
|
|||
output logic [P.XLEN-1:0] CSRUReadValM,
|
||||
input logic [4:0] SetFflagsM,
|
||||
output logic [2:0] FRM_REGW,
|
||||
output logic WriteFRMM, WriteFFLAGSM,
|
||||
output logic WriteFRMM, SetOrWriteFFLAGSM,
|
||||
output logic IllegalCSRUAccessM
|
||||
);
|
||||
|
||||
|
|
@ -48,7 +48,7 @@ module csru import cvw::*; #(parameter cvw_t P) (
|
|||
logic [4:0] FFLAGS_REGW;
|
||||
logic [2:0] NextFRMM;
|
||||
logic [4:0] NextFFLAGSM;
|
||||
logic SetOrWriteFFLAGSM;
|
||||
logic WriteFFLAGSM;
|
||||
|
||||
// Write enables
|
||||
assign WriteFRMM = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR);
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ LIBRARY_FILES :=
|
|||
|
||||
MARCH :=-march=rv64imfdc
|
||||
MABI :=-mabi=lp64d
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib
|
||||
LINKER :=$(ROOT)/linker1000.x
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ LIBRARY_FILES := crt0
|
|||
MARCH :=-march=rv64imfdc
|
||||
MABI :=-mabi=lp64d
|
||||
LINKER := ${ROOT}/linker8000-0000.x
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib
|
||||
|
||||
CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2
|
||||
CC=riscv64-unknown-elf-gcc
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ LIBRARY_FILES :=
|
|||
|
||||
MARCH :=-march=rv64imfdc
|
||||
MABI :=-mabi=lp64d
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib
|
||||
LINKER := ${ROOT}/linker.x
|
||||
|
||||
AFLAGS =$(MARCH) $(MABI) -W
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ LIBRARY_FILES :=
|
|||
|
||||
MARCH :=-march=rv64imfdc
|
||||
MABI :=-mabi=lp64d
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib
|
||||
LINKER :=$(ROOT)/linker1000.x
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ LIBRARY_FILES :=
|
|||
|
||||
MARCH :=-march=rv64imfdc
|
||||
MABI :=-mabi=lp64d
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib
|
||||
LINKER :=$(ROOT)/linker1000.x
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ LIBRARY_FILES :=
|
|||
|
||||
MARCH :=-march=rv64imfdc
|
||||
MABI :=-mabi=lp64d
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib
|
||||
LINKER :=$(ROOT)/linker1000.x
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ LIBRARY_FILES := crt0
|
|||
|
||||
MARCH :=-march=rv64imfdc
|
||||
MABI :=-mabi=lp64d
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib
|
||||
LINKER := ${ROOT}/linker8000-0000.x
|
||||
|
||||
CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv",
|
|||
"elf64-littleriscv")
|
||||
OUTPUT_ARCH(riscv)
|
||||
ENTRY(_start)
|
||||
SEARCH_DIR("/opt/riscv/riscv64-unknown-elf/lib");
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv",
|
|||
"elf64-littleriscv")
|
||||
OUTPUT_ARCH(riscv)
|
||||
ENTRY(_start)
|
||||
SEARCH_DIR("/opt/riscv/riscv64-unknown-elf/lib");
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv",
|
|||
"elf64-littleriscv")
|
||||
OUTPUT_ARCH(riscv)
|
||||
ENTRY(_start)
|
||||
SEARCH_DIR("/opt/riscv/riscv64-unknown-elf/lib");
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ LIBRARY_FILES := crt0
|
|||
MARCH :=-march=rv64imfdczicbom
|
||||
MABI :=-mabi=lp64d
|
||||
LINKER := ${ROOT}/linker8000-0000.x
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib
|
||||
|
||||
CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2
|
||||
CC=riscv64-unknown-elf-gcc
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ LIBRARY_FILES := crt0
|
|||
|
||||
MARCH :=-march=rv64ic
|
||||
MABI :=-mabi=lp64
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib
|
||||
LINKER := ${ROOT}/linker8000-0000.x
|
||||
|
||||
CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ LIBRARY_FILES := crt0
|
|||
|
||||
MARCH :=-march=rv64ic
|
||||
MABI :=-mabi=lp64
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib
|
||||
LINKER := ${ROOT}/linker8000-0000.x
|
||||
|
||||
CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ LIBRARY_FILES := crt0
|
|||
MARCH :=-march=rv64imfdczicbom
|
||||
MABI :=-mabi=lp64d
|
||||
LINKER := ${ROOT}/linker8000-0000.x
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib
|
||||
|
||||
CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2
|
||||
CC=riscv64-unknown-elf-gcc
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue