github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-06-28 01:32:49 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Add arty a7 debuggers for wfi and uart.

Browse source
This commit is contained in:
Rose Thompson 2024-12-02 14:20:57 -06:00
parent a772edcebb
commit e9b0b69696
4 changed files with 268 additions and 63 deletions
Download patch file Download diff file Expand all files Collapse all files

62
fpga/constraints/marked_debug.txt
View file

@ -5,39 +5,29 @@ wally/wallypipelinedcore.sv: logic InstrM
lsu/lsu.sv: logic IEUAdrM lsu/lsu.sv: logic IEUAdrM
lsu/lsu.sv: logic MemRWM lsu/lsu.sv: logic MemRWM
mmu/hptw.sv: logic SATP_REGW mmu/hptw.sv: logic SATP_REGW
uncore/uncore.sv: logic SDCCmd uncore/uartPC16550D.sv : logic MCR
uncore/uncore.sv: logic SDCCLK uncore/uartPC16550D.sv : logic FCR
uncore/uncore.sv: logic SDCIn uncore/uartPC16550D.sv : logic MSR
uncore/uncore.sv: logic SDCCS uncore/uartPC16550D.sv : logic DTRb
uncore/spi_apb.sv: logic InterruptPending uncore/uartPC16550D.sv : logic INTR
uncore/spi_apb.sv: logic TransmitFIFOWriteInc uncore/uartPC16550D.sv : logic RXRDYb
uncore/spi_apb.sv: logic TransmitFIFOEmpty uncore/uartPC16550D.sv : logic TXRDYb
uncore/spi_apb.sv: logic TransmitFIFOReadInc uncore/uartPC16550D.sv : logic RXerrIP
uncore/spi_apb.sv: logic TransmitLoad uncore/uartPC16550D.sv : logic IER
uncore/spi_apb.sv: logic ShiftEdge uncore/uartPC16550D.sv : logic LSR
uncore/spi_apb.sv: logic SampleEdge uncore/uartPC16550D.sv : logic SCR
uncore/spi_apb.sv: logic ReceiveShiftReg uncore/uartPC16550D.sv : statetype txstate
uncore/spi_apb.sv: logic TransmitReg uncore/uartPC16550D.sv : logic RBR
uncore/spi_apb.sv: logic ShiftIn uncore/uartPC16550D.sv : logic rxparityerr
uncore/spi_apb.sv: logic EndOfFrame uncore/uartPC16550D.sv : logic LCR
uncore/spi_apb.sv: logic TransmitRegLoaded uncore/uartPC16550D.sv : logic intrID
uncore/spi_apb.sv: logic TransmitData uncore/uartPC16550D.sv : logic rxdataavailintr
uncore/spi_apb.sv: logic ReceiveFIFOWriteInc uncore/uartPC16550D.sv : logic fifoenabled
uncore/spi_apb.sv: logic ReceiveFIFOReadInc uncore/uartPC16550D.sv : logic rxfifoentries
uncore/spi_apb.sv: logic ReceiveShiftRegEndian uncore/uartPC16550D.sv : logic txsrfull
uncore/spi_apb.sv: logic ReceiveWatermark uncore/uartPC16550D.sv : logic txhrfull
uncore/spi_apb.sv: logic ReceiveReadWatermarkLevel uncore/uartPC16550D.sv : logic txfifofull
uncore/spi_apb.sv: logic ReceiveData uncore/uartPC16550D.sv : logic txfifotail
uncore/spi_apb.sv: logic ReceiveFIFOFull uncore/uartPC16550D.sv : logic txfifohead
uncore/spi_apb.sv: logic ReceiveFIFOEmpty uncore/uartPC16550D.sv : logic rxfifotriggered
uncore/spi_controller.sv: logic SCLKenable uncore/uartPC16550D.sv : logic rxdataready
uncore/spi_controller.sv: statetype CurrState
uncore/spi_controller.sv: statetype NextState
uncore/spi_controller.sv: logic BitNum
uncore/spi_controller.sv: logic ContinueTransmit
uncore/spi_controller.sv: logic PhaseOneOffset
uncore/spi_controller.sv: logic SPICLK
uncore/spi_fifo.sv: logic rptr
uncore/spi_fifo.sv: logic rptrnext
uncore/spi_fifo.sv: logic raddr
uncore/spi_fifo.sv: logic waddr

59
fpga/constraints/marked_debug_spi.txt
View file

@ -5,32 +5,39 @@ wally/wallypipelinedcore.sv: logic InstrM
lsu/lsu.sv: logic IEUAdrM lsu/lsu.sv: logic IEUAdrM
lsu/lsu.sv: logic MemRWM lsu/lsu.sv: logic MemRWM
mmu/hptw.sv: logic SATP_REGW mmu/hptw.sv: logic SATP_REGW
uncore/spi_apb.sv: logic ShiftIn uncore/uncore.sv: logic SDCCmd
uncore/spi_apb.sv: logic ReceiveShiftReg uncore/uncore.sv: logic SDCCLK
uncore/spi_apb.sv: logic SCLKenable uncore/uncore.sv: logic SDCIn
uncore/spi_apb.sv: logic SampleEdge uncore/uncore.sv: logic SDCCS
uncore/spi_apb.sv: logic Active uncore/spi_apb.sv: logic InterruptPending
uncore/spi_apb.sv: statetype state uncore/spi_apb.sv: logic TransmitFIFOWriteInc
uncore/spi_apb.sv: typedef rsrstatetype uncore/spi_apb.sv: logic TransmitFIFOEmpty
uncore/spi_apb.sv: logic SPICLK uncore/spi_apb.sv: logic TransmitFIFOReadInc
uncore/spi_apb.sv: logic SPIOut uncore/spi_apb.sv: logic TransmitLoad
uncore/spi_apb.sv: logic SPICS
uncore/spi_apb.sv: logic SckMode
uncore/spi_apb.sv: logic SckDiv
uncore/spi_apb.sv: logic ShiftEdge uncore/spi_apb.sv: logic ShiftEdge
uncore/spi_apb.sv: logic TransmitShiftRegLoadSingleCycle uncore/spi_apb.sv: logic SampleEdge
uncore/spi_apb.sv: logic TransmitShiftReg uncore/spi_apb.sv: logic ReceiveShiftReg
uncore/spi_apb.sv: logic TransmitReg
uncore/spi_apb.sv: logic ShiftIn
uncore/spi_apb.sv: logic EndOfFrame
uncore/spi_apb.sv: logic TransmitRegLoaded
uncore/spi_apb.sv: logic TransmitData uncore/spi_apb.sv: logic TransmitData
uncore/spi_apb.sv: logic ReceiveData uncore/spi_apb.sv: logic ReceiveFIFOWriteInc
uncore/spi_apb.sv: logic ReceiveFIFOReadInc
uncore/spi_apb.sv: logic ReceiveShiftRegEndian uncore/spi_apb.sv: logic ReceiveShiftRegEndian
uncore/spi_apb.sv: logic TransmitShiftReg uncore/spi_apb.sv: logic ReceiveWatermark
uncore/spi_apb.sv: logic TransmitShift uncore/spi_apb.sv: logic ReceiveReadWatermarkLevel
uncore/spi_apb.sv: logic ReceiveShiftFullDelay uncore/spi_apb.sv: logic ReceiveData
uncore/spi_apb.sv: logic TransmitShiftEmpty uncore/spi_apb.sv: logic ReceiveFIFOFull
uncore/spi_apb.sv: logic ReceiveFIFOWriteFull uncore/spi_apb.sv: logic ReceiveFIFOEmpty
uncore/spi_apb.sv: logic ReceiveFIFOReadIncrement uncore/spi_controller.sv: logic SCLKenable
uncore/spi_apb.sv: logic ReceiveFIFOReadEmpty uncore/spi_controller.sv: statetype CurrState
uncore/spi_apb.sv: logic TransmitFIFOWriteIncrement uncore/spi_controller.sv: statetype NextState
uncore/spi_apb.sv: logic TransmitFIFOReadIncrement uncore/spi_controller.sv: logic BitNum
uncore/spi_apb.sv: logic TransmitFIFOWriteFull uncore/spi_controller.sv: logic ContinueTransmit
uncore/spi_apb.sv: logic TransmitFIFOReadEmpty uncore/spi_controller.sv: logic PhaseOneOffset
uncore/spi_controller.sv: logic SPICLK
uncore/spi_fifo.sv: logic rptr
uncore/spi_fifo.sv: logic rptrnext
uncore/spi_fifo.sv: logic raddr
uncore/spi_fifo.sv: logic waddr

208
fpga/constraints/small-debug-uart.xdc Normal file
View file

@ -0,0 +1,208 @@
create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
startgroup
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
endgroup
connect_debug_port u_ila_0/clk [get_nets CPUCLK]
set_property port_width 33 [get_debug_ports u_ila_0/probe0]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} } ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe4]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe5]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe6]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe7]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 5 [get_debug_ports u_ila_0/probe8]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[4]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe9]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe10]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/DTRb ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/INTR ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe13]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[3]}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txsrfull}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txhrfull}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RXRDYb ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifofull}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifoempty}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/TXRDYb ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RXerrIP} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe21]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe22]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe23]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe24]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 11 [get_debug_ports u_ila_0/probe25]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[7]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[8]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[9]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[10]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe26]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxparityerr} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe27]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe28]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe29]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxdataavailintr} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/fifoenabled} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
connect_debug_port u_ila_0/probe32 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifotriggered} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe33]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
connect_debug_port u_ila_0/probe33 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
connect_debug_port u_ila_0/probe34 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxdataready} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
connect_debug_port u_ila_0/probe35 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[3]}]]
# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
connect_debug_port dbg_hub/clk [get_nets CPUCLK]

2
fpga/generator/wally.tcl
View file

@ -98,7 +98,7 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v
if {$board=="ArtyA7"} { if {$board=="ArtyA7"} {
#source ../constraints/small-debug.xdc #source ../constraints/small-debug.xdc
#source ../constraints/small-debug-rvvi.xdc #source ../constraints/small-debug-rvvi.xdc
#source ../constraints/small-debug-spi.xdc source ../constraints/small-debug-uart.xdc
} else { } else {
#source ../constraints/vcu-small-debug.xdc #source ../constraints/vcu-small-debug.xdc
#source ../constraints/small-debug.xdc #source ../constraints/small-debug.xdc