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Fixed cvw-arch-verif Issue #553 about misaligned lr/sc needs to throw access fault

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David Harris 2025-04-08 16:38:26 -07:00
parent 25dbebb75c
commit e9ea1f59c4
1 changed files with 7 additions and 9 deletions
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16
src/mmu/mmu.sv
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@ -74,8 +74,7 @@ module mmu import cvw::*; #(parameter cvw_t P,
logic TLBPageFault; // Page fault from TLB
logic ReadNoAmoAccessM; // Read that is not part of atomic operation causes Load faults. Otherwise StoreAmo faults
logic [1:0] PBMemoryType; // PBMT field of PTE during TLB hit, or 00 otherwise
logic AmoMisalignedCausesAccessFaultM; // Misaligned AMO is not handled by hardware even with ZICCLSM, so it throws an access fault instead of misaligned with ZICCLSM
logic AmoAccessM; // AMO access detected when ReadAccessM and WriteAccessM are simultaneously asserted
logic AtomicMisalignedCausesAccessFaultM; // Misaligned atomics are not handled by hardware even with ZICCLSM, so it throws an access fault instead of misaligned with ZICCLSM
// only instantiate TLB if Virtual Memory is supported
if (P.VIRTMEM_SUPPORTED) begin:tlb
@ -127,7 +126,6 @@ module mmu import cvw::*; #(parameter cvw_t P,
end
assign ReadNoAmoAccessM = ReadAccessM & ~WriteAccessM;// AMO causes StoreAmo rather than Load fault
assign AmoAccessM = ReadAccessM & WriteAccessM;
// Misaligned faults
always_comb // exclusion-tag: immu-wordaccess
@ -141,15 +139,15 @@ module mmu import cvw::*; #(parameter cvw_t P,
assign LoadMisalignedFaultM = DataMisalignedM & ReadNoAmoAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable) & ~TLBMiss;
assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable) & ~TLBMiss; // Store and AMO both assert WriteAccess
// a misaligned Atomic causes an access fault rather than a misaligned fault if a misaligned load/store is handled in hardware
// this is subtle - see privileged spec 3.6.3.3
assign AtomicMisalignedCausesAccessFaultM = DataMisalignedM & AtomicAccessM & (P.ZICCLSM_SUPPORTED & Cacheable);
// Access faults
// If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~TLBMiss;
assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~TLBMiss;
// a misaligned AMO causes an access fault rather than a misaligned fault if a misaligned load/store is handled in hardware
// this is subtle - see privileged spec 3.6.3.3
// AMO is detected as ReadAccess & WriteAccess
assign AmoMisalignedCausesAccessFaultM = DataMisalignedM & AmoAccessM & (P.ZICCLSM_SUPPORTED & Cacheable);
assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM | AmoMisalignedCausesAccessFaultM) & ~TLBMiss;
assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM | AtomicMisalignedCausesAccessFaultM & ReadNoAmoAccessM) & ~TLBMiss;
assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM | AtomicMisalignedCausesAccessFaultM & WriteAccessM) & ~TLBMiss;
// Specify which type of page fault is occurring
assign InstrPageFaultF = TLBPageFault & ExecuteAccessF;