mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-24 22:07:12 -04:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
slmnemo
commit
ec214e4bf0
54 changed files with 2951 additions and 193 deletions
|
|
@ -17,6 +17,8 @@ git clone https://github.com/riscv-software-src/riscv-isa-sim
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cd riscv-isa-sim
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cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F
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<edit arch_test_target/spike/device/rv32i_m/F/Makefile.include line 35 and change --isa=rv32i to --isa=rv32if>
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cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv64i_m/D
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<edit arch_test_target/spike/device/rv64i_m/D/Makefile.include line 35 and change --isa=rv64i to --isa=rv64id>
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mkdir build
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cd build
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set RISCV=/cad/riscv/gcc/bin (or whatever your path is)
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|
|
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|||
166
tests/testgen/PIPELINE.py
Executable file
166
tests/testgen/PIPELINE.py
Executable file
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@ -0,0 +1,166 @@
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|||
#!/usr/bin/python3
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##################################
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# PIPELINE.py
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#
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# David_Harris@hmc.edu 27 October 2021
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#
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# Generate directed and random test vectors for RISC-V Design Validation.
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##################################
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##################################
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# libraries
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##################################
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from datetime import datetime
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from random import randint
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from random import seed
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from random import getrandbits
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##################################
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# functions
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##################################
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def twoscomp(a):
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amsb = a >> (xlen-1)
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alsbs = ((1 << (xlen-1)) - 1) & a
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if (amsb):
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asigned = a - (1<<xlen)
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else:
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asigned = a
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#print("a: " + str(a) + " amsb: "+str(amsb)+ " alsbs: " + str(alsbs) + " asigned: "+str(asigned))
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return asigned
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def computeExpected(a, b, test, xlen):
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asigned = twoscomp(a)
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bsigned = twoscomp(b)
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if (test == "ADD"):
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return a + b
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elif (test == "SUB"):
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return a - b
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elif (test == "SLT"):
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return asigned < bsigned
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elif (test == "SLTU"):
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return a < b
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elif (test == "XOR"):
|
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return a ^ b
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elif (test == "OR"):
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return a | b
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elif (test == "AND"):
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return a & b
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else:
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die("bad test name ", test)
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# exit(1)
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def randRegs():
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reg1 = randint(1,31)
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reg2 = randint(1,31)
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reg3 = randint(1,31)
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if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
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return randRegs()
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else:
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return reg1, reg2, reg3
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def writeVector(a, b, storecmd, xlen):
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global testnum
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expected = computeExpected(a, b, test, xlen)
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expected = expected % 2**xlen # drop carry if necessary
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if (expected < 0): # take twos complement
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expected = 2**xlen + expected
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reg1, reg2, reg3 = randRegs()
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lines = "\n# Testcase " + str(testnum) + ": rs1:x" + str(reg1) + "(" + formatstr.format(a)
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lines = lines + "), rs2:x" + str(reg2) + "(" +formatstr.format(b)
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lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n"
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lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
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lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
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lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n"
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lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
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lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n"
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f.write(lines)
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if (xlen == 32):
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line = formatrefstr.format(expected)+"\n"
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else:
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line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
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r.write(line)
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testnum = testnum+1
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|
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##################################
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# main body
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##################################
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|
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# change these to suite your tests
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instrs = ["ADD"] # "SUB", "XOR", "OR", "AND", "SLT", "SLTU", ]
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author = "David_Harris@hmc.edu"
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xlens = [32, 64]
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numrand = 1000
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|
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# setup
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seed(0) # make tests reproducible
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||||
|
||||
# generate files for each test
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for xlen in xlens:
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formatstrlen = str(int(xlen/4))
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formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
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formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
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if (xlen == 32):
|
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storecmd = "sw"
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wordsize = 4
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else:
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storecmd = "sd"
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wordsize = 8
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pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/"
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fname = pathname + "src/PIPELINE.S"
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testnum = 0
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||||
|
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# print custom header part
|
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f = open(fname, "w")
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||||
# r = open(refname, "w")
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line = "///////////////////////////////////////////\n"
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f.write(line)
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lines="// "+fname+ "\n// " + author + "\n"
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f.write(lines)
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line ="// Created " + str(datetime.now())
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f.write(line)
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|
||||
# insert generic header
|
||||
h = open("testgen_header.S", "r")
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for line in h:
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||||
f.write(line)
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|
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maxreg = 5
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for i in range(numrand):
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instr = instrs[randint(0,len(instrs)-1)]
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reg1 = randint(0,maxreg)
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reg2 = randint(1,maxreg)
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reg3 = randint(1,maxreg)
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line = instr + " x" +str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n"
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f.write(line)
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||||
|
||||
for i in range(1,maxreg+1):
|
||||
line = storecmd + " x" + str(i) + ", " + str(wordsize*(i-1)) + "(x8)\n"
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||||
f.write(line)
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||||
|
||||
# print directed and random test vectors
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||||
# for a in corners:
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||||
# for b in corners:
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||||
# writeVector(a, b, storecmd, xlen)
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# for i in range(0,numrand):
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# a = getrandbits(xlen)
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# b = getrandbits(xlen)
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# writeVector(a, b, storecmd, xlen)
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||||
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||||
|
||||
# print footer
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||||
h = open("testgen_footer.S", "r")
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||||
for line in h:
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||||
f.write(line)
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||||
|
||||
# Finish
|
||||
# lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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# lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
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f.write(lines)
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f.close()
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||||
# r.close()
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||||
|
||||
|
||||
|
||||
|
||||
46
tests/testgen/testgen_footer.S
Normal file
46
tests/testgen/testgen_footer.S
Normal file
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|
@ -0,0 +1,46 @@
|
|||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
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||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
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||||
rvtest_data:
|
||||
.word 0xbabecafe
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||||
RVTEST_DATA_END
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||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
|
||||
|
||||
signature_x8_0:
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||||
.fill 0*(XLEN/32),4,0xdeadbeef
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||||
|
||||
|
||||
signature_x8_1:
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||||
.fill 19*(XLEN/32),4,0xdeadbeef
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||||
|
||||
|
||||
signature_x1_0:
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||||
.fill 256*(XLEN/32),4,0xdeadbeef
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||||
|
||||
|
||||
signature_x1_1:
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||||
.fill 256*(XLEN/32),4,0xdeadbeef
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||||
|
||||
|
||||
signature_x1_2:
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||||
.fill 148*(XLEN/32),4,0xdeadbeef
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||||
|
||||
#ifdef rvtest_mtrap_routine
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||||
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||||
mtrap_sigptr:
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||||
.fill 64*(XLEN/32),4,0xdeadbeef
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||||
|
||||
#endif
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||||
|
||||
#ifdef rvtest_gpr_save
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||||
|
||||
gpr_save:
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||||
.fill 32*(XLEN/32),4,0xdeadbeef
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||||
|
||||
#endif
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||||
|
||||
RVMODEL_DATA_END
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||||
26
tests/testgen/testgen_header.S
Normal file
26
tests/testgen/testgen_header.S
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
RVTEST_SIGBASE( x8,signature_x8_1)
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||||
|
|
@ -87,7 +87,7 @@ simulate:
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|||
run -C $(SUITEDIR)
|
||||
|
||||
verify: simulate
|
||||
riscv-test-env/verify.sh
|
||||
# riscv-test-env/verify.sh # dmh 1 November 2021 removed because these tests don't have expected values
|
||||
|
||||
postverify:
|
||||
ifeq ($(wildcard $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh),)
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
# Description: Makefrag for RV32I architectural tests
|
||||
|
||||
rv32i_sc_tests = \
|
||||
|
||||
PIPELINE \
|
||||
|
||||
rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,3 @@
|
|||
include ../../Makefile.include
|
||||
|
||||
$(eval $(call compile_template,-march=rv64id -mabi=lp64 -DXLEN=$(XLEN)))
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
# RISC-V Architecture Test RV64IM Makefrag
|
||||
#
|
||||
# Copyright (c) 2018, Imperas Software Ltd.
|
||||
# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
# * Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
# * Neither the name of the Imperas Software Ltd. nor the
|
||||
# names of its contributors may be used to endorse or promote products
|
||||
# derived from this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
|
||||
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Description: Makefrag for RV64IM architectural tests
|
||||
|
||||
rv64im_sc_tests = \
|
||||
|
||||
rv64im_tests = $(addsuffix .elf, $(rv64im_sc_tests))
|
||||
|
||||
target_tests += $(rv64im_tests)
|
||||
|
|
@ -29,6 +29,7 @@
|
|||
|
||||
rv64i_sc_tests = \
|
||||
add-01 \
|
||||
PIPELINE \
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -62,7 +62,8 @@ for(my $i=0; $i<=$#ARGV; $i++) {
|
|||
}
|
||||
if (/Disassembly of section .data:/) { $mode = 1;}
|
||||
} elsif ($mode == 1) { # Parse data segment
|
||||
if (/^\s*(\S\S\S\S\S\S\S\S):\s+(.*)/) {
|
||||
# if (/^\s*(\S\S\S\S\S\S\S\S):\s+(.*)/) { # changed to \t 30 Oct 2021 dmh to fix parsing issue in d_fmadd_b17
|
||||
if (/^\s*(\S\S\S\S\S\S\S\S):\t+(.*)/) {
|
||||
$address = &fixadr($1);
|
||||
# print "addresss $address maxaddress $maxaddress\n";
|
||||
if ($address > $maxaddress) { $maxaddress = $address; }
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
source genSettings.sh
|
||||
tcpPort=1236
|
||||
|
||||
instrs=10000000
|
||||
instrs=480000000
|
||||
checkOutDir="$outDir/checkpoint$instrs"
|
||||
checkIntermedDir="$checkOutDir/intermediate-outputs"
|
||||
|
||||
|
|
@ -32,7 +32,7 @@ then
|
|||
# Post-Process GDB outputs
|
||||
./parseState.py "$checkOutDir"
|
||||
./fix_mem.py "$checkIntermedDir/ramGDB.txt" "$checkOutDir/ram.txt"
|
||||
tail -n+$instrs "$outDir/$traceFile" > "$checkOutDir/$traceFile"
|
||||
tail -n+$($instrs+1) "$outDir/$traceFile" > "$checkOutDir/$traceFile"
|
||||
else
|
||||
echo "You can change the number of instructions by editing the \"instrs\" variable in this script."
|
||||
echo "Have a nice day!"
|
||||
|
|
|
|||
|
|
@ -60,20 +60,26 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
|
|||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
|
||||
add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE
|
||||
add wave -noupdate -group {Execution Stage} /testbench/InstrEName
|
||||
add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
|
||||
add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
|
||||
add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
|
||||
add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM
|
||||
add wave -noupdate -group {Memory Stage} /testbench/InstrMName
|
||||
add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM
|
||||
add wave -noupdate -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/PCW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/textE
|
||||
add wave -noupdate -expand -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/textM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
|
||||
add wave -noupdate -expand -group {WriteBack stage} /testbench/checkInstrW
|
||||
add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrValidW
|
||||
add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW
|
||||
add wave -noupdate -expand -group {WriteBack stage} /testbench/ExpectedPCW
|
||||
add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrW
|
||||
add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrWName
|
||||
add wave -noupdate -expand -group {WriteBack stage} /testbench/textW
|
||||
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
|
||||
|
|
@ -484,7 +490,6 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/p
|
|||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
|
||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM
|
||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM
|
||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/line
|
||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM
|
||||
add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/hart/hzu/TrapM
|
||||
add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW
|
||||
|
|
@ -510,7 +515,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/memwrite
|
|||
add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
|
||||
add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {229 ns} 0}
|
||||
WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {5672440 ns} 0}
|
||||
quietly wave cursor active 2
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 314
|
||||
|
|
@ -526,4 +531,4 @@ configure wave -griddelta 40
|
|||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {182 ns} {330 ns}
|
||||
WaveRestoreZoom {5672937 ns} {5673085 ns}
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ def getBuildrootTC(short):
|
|||
BRgrepstr=str(MAX_EXPECTED)+" instructions"
|
||||
return TestCase(name="buildroot",cmd=BRcmd,grepstr=BRgrepstr)
|
||||
|
||||
tests64 = ["arch64i", "arch64priv", "arch64c", "arch64m", "imperas64i", "imperas64p", "imperas64mmu", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c"] #, "testsBP64"]
|
||||
tests64 = ["wally64i", "arch64i", "arch64priv", "arch64c", "arch64m", "imperas64i", "imperas64p", "imperas64mmu", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c"] #, "testsBP64"]
|
||||
for test in tests64:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
|
|
@ -49,7 +49,7 @@ for test in tests64:
|
|||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
#tests32 = ["arch32i", "arch32priv", "arch32c", "arch32m", "arch32f", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"]
|
||||
tests32 = ["arch32i", "arch32priv", "arch32c", "arch32m", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"]
|
||||
tests32 = ["wally32i", "arch32i", "arch32priv", "arch32c", "arch32m", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"]
|
||||
for test in tests32:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
|
|
|
|||
|
|
@ -30,4 +30,4 @@ echo "INSTR_LIMIT = ${INSTR_LIMIT}"
|
|||
echo "INSTR_WAVEON = ${INSTR_WAVEON}"
|
||||
echo "CHECKPOINT = ${CHECKPOINT}"
|
||||
|
||||
vsim -do wally-buildroot.do $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT
|
||||
vsim -do "do ./wally-buildroot.do $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT"
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
vsim -c <<!
|
||||
do wally-pipelined-batch.do rv32g arch32f
|
||||
do wally-pipelined-batch.do rv64g arch64d
|
||||
!
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ module cachereplacementpolicy
|
|||
ReplacementBits[index] <= '0;
|
||||
end else begin
|
||||
RAdrD <= RAdr;
|
||||
MemPAdrMD <= MemPAdrMD;
|
||||
MemPAdrMD <= MemPAdrM;
|
||||
LRUWriteEnD <= LRUWriteEn;
|
||||
NewReplacementD <= NewReplacement;
|
||||
if (LRUWriteEnD) begin
|
||||
|
|
@ -84,6 +84,38 @@ module cachereplacementpolicy
|
|||
|
||||
end else if (NUMWAYS == 4) begin : FourWay
|
||||
|
||||
|
||||
// VictimWay is a function only of the current value of the LRU.
|
||||
// binary encoding
|
||||
//assign VictimWay[0] = BlockReplacementBits[2] ? BlockReplacementBits[1] : BlockReplacementBits[0];
|
||||
//assign VictimWay[1] = BlockReplacementBits[2];
|
||||
|
||||
// 1 hot encoding
|
||||
//| WayHit | LRU 2 | LRU 1 | LRU 0 |
|
||||
//|--------+-------+-------+-------|
|
||||
//| 0000 | - | - | - |
|
||||
//| 0001 | 1 | - | 1 |
|
||||
//| 0010 | 1 | - | 0 |
|
||||
//| 0100 | 0 | 1 | - |
|
||||
//| 1000 | 0 | 0 | - |
|
||||
|
||||
assign VictimWay[0] = ~BlockReplacementBits[2] & ~BlockReplacementBits[0];
|
||||
assign VictimWay[1] = ~BlockReplacementBits[2] & BlockReplacementBits[0];
|
||||
assign VictimWay[2] = BlockReplacementBits[2] & ~BlockReplacementBits[1];
|
||||
assign VictimWay[3] = BlockReplacementBits[2] & BlockReplacementBits[1];
|
||||
|
||||
// New LRU bits which are updated is function only of the WayHit.
|
||||
// However the not updated bits come from the old LRU.
|
||||
assign LRUEn[2] = |WayHit;
|
||||
assign LRUEn[1] = WayHit[3] | WayHit[2];
|
||||
assign LRUEn[0] = WayHit[1] | WayHit[0];
|
||||
|
||||
assign LRUMask[2] = WayHit[1] | WayHit[0];
|
||||
assign LRUMask[1] = WayHit[2];
|
||||
assign LRUMask[0] = WayHit[0];
|
||||
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
|
||||
// selects
|
||||
assign LRUEn[2] = 1'b1;
|
||||
assign LRUEn[1] = WayHit[3];
|
||||
|
|
@ -93,16 +125,19 @@ module cachereplacementpolicy
|
|||
assign LRUMask[0] = WayHit[1];
|
||||
assign LRUMask[1] = WayHit[3];
|
||||
assign LRUMask[2] = WayHit[3] | WayHit[2];
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
for(index = 0; index < NUMWAYS-1; index++)
|
||||
assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : BlockReplacementBits[index];
|
||||
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
assign EncVicWay[1] = BlockReplacementBits[2];
|
||||
assign EncVicWay[0] = BlockReplacementBits[2] ? BlockReplacementBits[0] : BlockReplacementBits[1];
|
||||
|
||||
onehotdecoder #(2)
|
||||
waydec(.bin(EncVicWay),
|
||||
.decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3]}));
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
end else if (NUMWAYS == 8) begin : EightWay
|
||||
|
||||
|
|
|
|||
6
wally-pipelined/src/cache/dcache.sv
vendored
6
wally-pipelined/src/cache/dcache.sv
vendored
|
|
@ -142,6 +142,8 @@ module dcache
|
|||
|
||||
logic LRUWriteEn;
|
||||
|
||||
logic [NUMWAYS-1:0] VDWriteEnableWay;
|
||||
|
||||
// Read Path CPU (IEU) side
|
||||
|
||||
mux4 #(INDEXLEN)
|
||||
|
|
@ -167,7 +169,7 @@ module dcache
|
|||
.WAdr,
|
||||
.PAdr(MemPAdrM),
|
||||
.WriteEnable(SRAMWayWriteEnable),
|
||||
.VDWriteEnable,
|
||||
.VDWriteEnable(VDWriteEnableWay),
|
||||
.WriteWordEnable(SRAMWordEnable),
|
||||
.TagWriteEnable(SRAMBlockWayWriteEnableM),
|
||||
.WriteData(SRAMWriteData),
|
||||
|
|
@ -329,6 +331,8 @@ module dcache
|
|||
.d(NextFlushWay),
|
||||
.q(FlushWay));
|
||||
|
||||
assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}};
|
||||
|
||||
assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
|
||||
|
||||
assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ module fpudivsqrtrecur (
|
|||
// Special Cases
|
||||
// *** shift to handle denorms in hardware
|
||||
|
||||
assign FDivSqrtResSign = FDivE & (XSgnE ^ YSgnE); // Sign is negative for division if inputs have opposite signs
|
||||
assign FDivSqrtResSgn = FDivE & (XSgnE ^ YSgnE); // Sign is negative for division if inputs have opposite signs
|
||||
|
||||
always_comb begin
|
||||
if (FSqrtE & XSgnE | FDivE & XZeroE & YZeroE | XNaNE | FDivE & YNaNE) FDivSqrtResM = 0; // ***replace with NAN; // *** which one
|
||||
|
|
|
|||
|
|
@ -65,6 +65,9 @@ module intdiv #(parameter WIDTH=64)
|
|||
logic D_NegOne;
|
||||
logic Max_N;
|
||||
|
||||
logic otfzerov;
|
||||
logic tcQ;
|
||||
logic tcR;
|
||||
|
||||
// Check if negative (two's complement)
|
||||
// If so, convert to positive
|
||||
|
|
@ -184,6 +187,8 @@ module divide4 #(parameter WIDTH=64)
|
|||
logic [WIDTH+3:0] SumR, CarryR;
|
||||
logic [WIDTH:0] Qt;
|
||||
|
||||
logic ulp;
|
||||
|
||||
// Create one's complement values of Divisor (for q*D)
|
||||
assign divi1 = {3'h0, op2, 1'b0};
|
||||
assign divi2 = {2'h0, op2, 2'b0};
|
||||
|
|
|
|||
|
|
@ -154,9 +154,30 @@ module wallypipelinedhart (
|
|||
logic BreakpointFaultM, EcallFaultM;
|
||||
|
||||
|
||||
ifu ifu(.InstrInF(InstrRData),
|
||||
.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
|
||||
.*); // instruction fetch unit: PC, branch prediction, instruction cache
|
||||
ifu ifu(
|
||||
.clk, .reset,
|
||||
.StallF, .StallD, .StallE, .StallM, .StallW,
|
||||
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF, .InstrReadF, .ICacheStallF,
|
||||
.PCLinkE, .PCSrcE, .PCTargetE, .PCE,
|
||||
.BPPredWrongE,
|
||||
.RetM, .TrapM,
|
||||
.PrivilegedNextPCM, .InvalidateICacheM,
|
||||
.InstrD, .InstrM,
|
||||
.PCM, .InstrClassM,
|
||||
.BPPredDirWrongM,.BTBPredPCWrongM,.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
|
||||
.IllegalBaseInstrFaultD, .ITLBInstrPageFaultF, .IllegalIEUInstrFaultD,
|
||||
.InstrMisalignedFaultM, .InstrMisalignedAdrM,
|
||||
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
|
||||
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
|
||||
.ITLBWriteF, .ITLBFlushF,
|
||||
.WalkerInstrPageFaultF,
|
||||
.ITLBMissF,
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||
.InstrAccessFaultF
|
||||
|
||||
); // instruction fetch unit: PC, branch prediction, instruction cache
|
||||
|
||||
|
||||
ieu ieu(.*); // integer execution unit: integer register file, datapath and controller
|
||||
|
||||
|
|
|
|||
|
|
@ -103,30 +103,35 @@ module testbench();
|
|||
string checkpointDir;
|
||||
logic [1:0] initPriv;
|
||||
// Signals used to parse the trace file
|
||||
integer data_file_all;
|
||||
string name;
|
||||
integer matchCount;
|
||||
string line;
|
||||
logic [`XLEN-1:0] ExpectedPCM;
|
||||
logic [31:0] ExpectedInstrM;
|
||||
string textM;
|
||||
string token;
|
||||
string ExpectedTokens [31:0];
|
||||
integer index;
|
||||
integer StartIndex, EndIndex;
|
||||
integer TokenIndex;
|
||||
integer MarkerIndex;
|
||||
integer NumCSRM;
|
||||
`define DECLARE_TRACE_SCANNER_SIGNALS(STAGE) \
|
||||
integer traceFile``STAGE; \
|
||||
integer matchCount``STAGE; \
|
||||
string line``STAGE; \
|
||||
string token``STAGE; \
|
||||
string ExpectedTokens``STAGE [31:0]; \
|
||||
integer index``STAGE; \
|
||||
integer StartIndex``STAGE, EndIndex``STAGE; \
|
||||
integer TokenIndex``STAGE; \
|
||||
integer MarkerIndex``STAGE; \
|
||||
integer NumCSR``STAGE; \
|
||||
logic [`XLEN-1:0] ExpectedPC``STAGE; \
|
||||
logic [31:0] ExpectedInstr``STAGE; \
|
||||
string text``STAGE; \
|
||||
string MemOp``STAGE; \
|
||||
string RegWrite``STAGE; \
|
||||
integer ExpectedRegAdr``STAGE; \
|
||||
logic [`XLEN-1:0] ExpectedRegValue``STAGE; \
|
||||
logic [`XLEN-1:0] ExpectedMemAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
|
||||
string ExpectedCSRArray``STAGE[10:0]; \
|
||||
logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0];
|
||||
`DECLARE_TRACE_SCANNER_SIGNALS(E)
|
||||
`DECLARE_TRACE_SCANNER_SIGNALS(M)
|
||||
integer NextMIPexpected;
|
||||
integer NextMepcExpected;
|
||||
// Memory stage expected values from trace
|
||||
logic checkInstrM;
|
||||
integer MIPexpected;
|
||||
string RegWriteM;
|
||||
integer ExpectedRegAdrM;
|
||||
logic [`XLEN-1:0] ExpectedRegValueM;
|
||||
string MemOpM;
|
||||
logic [`XLEN-1:0] ExpectedMemAdrM, ExpectedMemReadDataM, ExpectedMemWriteDataM;
|
||||
string ExpectedCSRArrayM[10:0];
|
||||
logic [`XLEN-1:0] ExpectedCSRArrayValueM[10:0];
|
||||
string name;
|
||||
logic [`AHBW-1:0] readDataExpected;
|
||||
// Write back stage expected values from trace
|
||||
logic checkInstrW;
|
||||
|
|
@ -148,6 +153,11 @@ module testbench();
|
|||
integer NumCSRPostWIndex;
|
||||
logic [`XLEN-1:0] InstrCountW;
|
||||
integer RequestDelayedMIP;
|
||||
integer ForceMIPFuture;
|
||||
integer CSRIndex;
|
||||
longint MepcExpected;
|
||||
integer CheckMIPFutureE;
|
||||
integer CheckMIPFutureM;
|
||||
// Useful Aliases
|
||||
`define RF dut.hart.ieu.dp.regf.rf
|
||||
`define PC dut.hart.ifu.pcreg.q
|
||||
|
|
@ -292,13 +302,15 @@ module testbench();
|
|||
ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"};
|
||||
if (CHECKPOINT==0) begin // normal
|
||||
$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
|
||||
data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
|
||||
traceFileM = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
|
||||
traceFileE = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
|
||||
InstrCountW = '0;
|
||||
end else begin // checkpoint
|
||||
$sformat(checkpointDir,"checkpoint%0d/",CHECKPOINT);
|
||||
checkpointDir = {`LINUX_TEST_VECTORS,checkpointDir};
|
||||
$readmemh({checkpointDir,"ram.txt"}, dut.uncore.dtim.RAM);
|
||||
data_file_all = $fopen({checkpointDir,"all.txt"}, "r");
|
||||
traceFileE = $fopen({checkpointDir,"all.txt"}, "r");
|
||||
traceFileM = $fopen({checkpointDir,"all.txt"}, "r");
|
||||
InstrCountW = CHECKPOINT;
|
||||
// manual checkpoint initializations that don't neatly fit into MACRO
|
||||
force {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV} = initMSTATUS[0][22:17];
|
||||
|
|
@ -319,8 +331,12 @@ module testbench();
|
|||
release `INSTRET;
|
||||
release `CURR_PRIV;
|
||||
end
|
||||
// Get the E-stage trace reader ahead of the M-stage trace reader
|
||||
matchCountE = $fgets(lineE,traceFileE);
|
||||
end
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////// CORE /////////////////////////////////////
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -333,92 +349,156 @@ module testbench();
|
|||
|
||||
// step 0: read the expected state
|
||||
assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM;
|
||||
`define SCAN_NEW_INSTR_FROM_TRACE(STAGE) \
|
||||
// always check PC, instruction bits \
|
||||
if (checkInstrM) begin \
|
||||
// read 1 line of the trace file \
|
||||
matchCount``STAGE = $fgets(line``STAGE, traceFile``STAGE); \
|
||||
if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \
|
||||
// extract PC, Instr \
|
||||
matchCount``STAGE = $sscanf(line``STAGE, "%x %x %s", ExpectedPC``STAGE, ExpectedInstr``STAGE, text``STAGE); \
|
||||
\
|
||||
// for the life of me I cannot get any build in C or C++ string parsing functions/methods to work. \
|
||||
// strtok was the best idea but it cannot be used correctly as system verilog does not have null \
|
||||
// terminated strings. \
|
||||
\
|
||||
// Just going to do this char by char. \
|
||||
StartIndex``STAGE = 0; \
|
||||
TokenIndex``STAGE = 0; \
|
||||
//$display("len = %d", line``STAGE.len()); \
|
||||
for(index``STAGE = 0; index``STAGE < line``STAGE.len(); index``STAGE++) begin \
|
||||
//$display("char = %s", line``STAGE[index]); \
|
||||
if (line``STAGE[index``STAGE] == " " || line``STAGE[index``STAGE] == "\n") begin \
|
||||
EndIndex``STAGE = index``STAGE; \
|
||||
ExpectedTokens``STAGE[TokenIndex``STAGE] = line``STAGE.substr(StartIndex``STAGE, EndIndex``STAGE-1); \
|
||||
//$display("In Tokenizer %s", line``STAGE.substr(StartIndex, EndIndex-1)); \
|
||||
StartIndex``STAGE = EndIndex``STAGE + 1; \
|
||||
TokenIndex``STAGE++; \
|
||||
end \
|
||||
end \
|
||||
\
|
||||
MarkerIndex``STAGE = 3; \
|
||||
NumCSR``STAGE = 0; \
|
||||
MemOp``STAGE = ""; \
|
||||
RegWrite``STAGE = ""; \
|
||||
\
|
||||
#2; \
|
||||
\
|
||||
while(TokenIndex``STAGE > MarkerIndex``STAGE) begin \
|
||||
// parse the GPR \
|
||||
if (ExpectedTokens``STAGE[MarkerIndex``STAGE] == "GPR") begin \
|
||||
RegWrite``STAGE = ExpectedTokens``STAGE[MarkerIndex``STAGE]; \
|
||||
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%d", ExpectedRegAdr``STAGE); \
|
||||
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+2], "%x", ExpectedRegValue``STAGE); \
|
||||
MarkerIndex``STAGE += 3; \
|
||||
// parse memory address, read data, and/or write data \
|
||||
end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE].substr(0, 2) == "Mem") begin \
|
||||
MemOp``STAGE = ExpectedTokens``STAGE[MarkerIndex``STAGE]; \
|
||||
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedMemAdr``STAGE); \
|
||||
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+2], "%x", ExpectedMemWriteData``STAGE); \
|
||||
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+3], "%x", ExpectedMemReadData``STAGE); \
|
||||
MarkerIndex``STAGE += 4; \
|
||||
// parse CSRs, because there are 1 or more CSRs after the CSR token \
|
||||
// we check if the CSR token or the number of CSRs is greater than 0. \
|
||||
// if so then we want to parse for a CSR. \
|
||||
end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR" || NumCSR``STAGE > 0) begin \
|
||||
if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR") begin \
|
||||
// all additional CSR's won't have this token. \
|
||||
MarkerIndex``STAGE++; \
|
||||
end \
|
||||
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE], "%s", ExpectedCSRArray``STAGE[NumCSR``STAGE]); \
|
||||
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedCSRArrayValue``STAGE[NumCSR``STAGE]); \
|
||||
MarkerIndex``STAGE += 2; \
|
||||
if(`"STAGE`"=="E") begin \
|
||||
// match MIP to QEMU's because interrupts are imprecise \
|
||||
if(ExpectedCSRArrayE[NumCSRE].substr(0, 2) == "mip") begin \
|
||||
CheckMIPFutureE = 1; \
|
||||
NextMIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \
|
||||
end \
|
||||
// $display("%tn: ExpectedCSRArrayM[7] (MEPC) = %x",$time,ExpectedCSRArrayM[7]); \
|
||||
// $display("%tn: ExpectedPCM = %x",$time,ExpectedPCM); \
|
||||
// // if PC does not equal MEPC, request delayed MIP is True \
|
||||
// if(ExpectedPCM != ExpectedCSRArrayM[7]) begin \
|
||||
// RequestDelayedMIP = 1; \
|
||||
// end else begin \
|
||||
// $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueM[NumCSRM]); \
|
||||
// MIPexpected = ExpectedCSRArrayValueM[NumCSRM]; \
|
||||
// force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; \
|
||||
// end \
|
||||
// end \
|
||||
// $display("%tns: ExpectedCSRArrayM::: %p",$time,ExpectedCSRArrayM); \
|
||||
if(ExpectedCSRArrayE[NumCSRE].substr(0,3) == "mepc") begin \
|
||||
$display("hello! we are here."); \
|
||||
MepcExpected = ExpectedCSRArrayValueE[NumCSRE]; \
|
||||
$display("%tns: MepcExpected: %x",$time,MepcExpected); \
|
||||
end \
|
||||
end \
|
||||
\
|
||||
NumCSR``STAGE++; \
|
||||
end \
|
||||
end \
|
||||
if(`"STAGE`"=="M") begin \
|
||||
// override on special conditions \
|
||||
if (ExpectedMemAdrM == 'h10000005) begin \
|
||||
//$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW); \
|
||||
force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
|
||||
end \
|
||||
if(textM.substr(0,5) == "rdtime") begin \
|
||||
//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW); \
|
||||
force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \
|
||||
end \
|
||||
end \
|
||||
end \
|
||||
|
||||
always @(negedge clk) begin
|
||||
// always check PC, instruction bits
|
||||
if (checkInstrM) begin
|
||||
// read 1 line of the trace file
|
||||
matchCount = $fgets(line, data_file_all);
|
||||
if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line);
|
||||
// extract PC, Instr
|
||||
matchCount = $sscanf(line, "%x %x %s", ExpectedPCM, ExpectedInstrM, textM);
|
||||
//$display("matchCount %d, PCM %x ExpectedInstrM %x textM %x", matchCount, ExpectedPCM, ExpectedInstrM, textM);
|
||||
|
||||
// for the life of me I cannot get any build in C or C++ string parsing functions/methods to work.
|
||||
// strtok was the best idea but it cannot be used correctly as system verilog does not have null
|
||||
// terminated strings.
|
||||
|
||||
// Just going to do this char by char.
|
||||
StartIndex = 0;
|
||||
TokenIndex = 0;
|
||||
//$display("len = %d", line.len());
|
||||
for(index = 0; index < line.len(); index++) begin
|
||||
//$display("char = %s", line[index]);
|
||||
if (line[index] == " " || line[index] == "\n") begin
|
||||
EndIndex = index;
|
||||
ExpectedTokens[TokenIndex] = line.substr(StartIndex, EndIndex-1);
|
||||
//$display("In Tokenizer %s", line.substr(StartIndex, EndIndex-1));
|
||||
StartIndex = EndIndex + 1;
|
||||
TokenIndex++;
|
||||
end
|
||||
`SCAN_NEW_INSTR_FROM_TRACE(E)
|
||||
end
|
||||
|
||||
MarkerIndex = 3;
|
||||
NumCSRM = 0;
|
||||
MemOpM = "";
|
||||
RegWriteM = "";
|
||||
|
||||
#2;
|
||||
|
||||
while(TokenIndex > MarkerIndex) begin
|
||||
// parse the GPR
|
||||
if (ExpectedTokens[MarkerIndex] == "GPR") begin
|
||||
RegWriteM = ExpectedTokens[MarkerIndex];
|
||||
matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%d", ExpectedRegAdrM);
|
||||
matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedRegValueM);
|
||||
MarkerIndex += 3;
|
||||
// parse memory address, read data, and/or write data
|
||||
end else if(ExpectedTokens[MarkerIndex].substr(0, 2) == "Mem") begin
|
||||
MemOpM = ExpectedTokens[MarkerIndex];
|
||||
matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedMemAdrM);
|
||||
matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedMemWriteDataM);
|
||||
matchCount = $sscanf(ExpectedTokens[MarkerIndex+3], "%x", ExpectedMemReadDataM);
|
||||
MarkerIndex += 4;
|
||||
// parse CSRs, because there are 1 or more CSRs after the CSR token
|
||||
// we check if the CSR token or the number of CSRs is greater than 0.
|
||||
// if so then we want to parse for a CSR.
|
||||
end else if(ExpectedTokens[MarkerIndex] == "CSR" || NumCSRM > 0) begin
|
||||
if(ExpectedTokens[MarkerIndex] == "CSR") begin
|
||||
// all additional CSR's won't have this token.
|
||||
MarkerIndex++;
|
||||
always @(negedge clk) begin
|
||||
`SCAN_NEW_INSTR_FROM_TRACE(M)
|
||||
end
|
||||
matchCount = $sscanf(ExpectedTokens[MarkerIndex], "%s", ExpectedCSRArrayM[NumCSRM]);
|
||||
matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedCSRArrayValueM[NumCSRM]);
|
||||
MarkerIndex += 2;
|
||||
// match MIP to QEMU's because interrupts are imprecise
|
||||
if(ExpectedCSRArrayM[NumCSRM].substr(0, 2) == "mip") begin
|
||||
$display("%tn: ExpectedCSRArrayM[7] (MEPC) = %x",$time,ExpectedCSRArrayM[7]);
|
||||
|
||||
// MIP spoofing
|
||||
always @(posedge clk) begin
|
||||
#1;
|
||||
if(CheckMIPFutureE) CheckMIPFutureE <= 0;
|
||||
CheckMIPFutureM <= CheckMIPFutureE;
|
||||
if(CheckMIPFutureM) begin
|
||||
if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin
|
||||
RequestDelayedMIP = 1;
|
||||
$display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected);
|
||||
end else begin // update MIP immediately
|
||||
$display("%tns: Updating MIP to %x",$time,NextMIPexpected);
|
||||
MIPexpected = NextMIPexpected;
|
||||
force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
|
||||
end
|
||||
$display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM);
|
||||
$display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM);
|
||||
$display("%tn: ExpectedTokens = %p",$time,ExpectedTokensM);
|
||||
$display("%tn: MepcExpected = %x",$time,MepcExpected);
|
||||
$display("%tn: ExpectedPCM = %x",$time,ExpectedPCM);
|
||||
// if PC does not equal MEPC, request delayed MIP is True
|
||||
if(ExpectedPCM != ExpectedCSRArrayM[7]) begin
|
||||
$display("%tns: Difference/multiplication thing: %x",$time,(MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM));
|
||||
$display("%tn: ExpectedCSRArrayM[NumCSRM] %x",$time,ExpectedCSRArrayM[NumCSRM]);
|
||||
$display("%tn: ExpectedCSRArrayValueM[NumCSRM] %x",$time,ExpectedCSRArrayValueM[NumCSRM]);
|
||||
|
||||
if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin
|
||||
RequestDelayedMIP = 1;
|
||||
$display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected);
|
||||
end else begin
|
||||
$display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueM[NumCSRM]);
|
||||
MIPexpected = ExpectedCSRArrayValueM[NumCSRM];
|
||||
$display("%tns: Updating MIP to %x",$time,NextMIPexpected);
|
||||
MIPexpected = NextMIPexpected;
|
||||
force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
|
||||
end
|
||||
end
|
||||
NumCSRM++;
|
||||
end
|
||||
end
|
||||
// override on special conditions
|
||||
if (ExpectedMemAdrM == 'h10000005) begin
|
||||
//$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW);
|
||||
force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM;
|
||||
end
|
||||
if(textM.substr(0,5) == "rdtime") begin
|
||||
//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW);
|
||||
force dut.uncore.clint.clint.MTIME = ExpectedRegValueM;
|
||||
end
|
||||
if(RequestDelayedMIP) begin
|
||||
$display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.csr.genblk1.csrm.MEPC_REGW);
|
||||
$display("%tns: Updating MIP to %x",$time,NextMIPexpected);
|
||||
$display("%tns: MepcExpected %x",$time,MepcExpected);
|
||||
MIPexpected = NextMIPexpected;
|
||||
force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
|
||||
$display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.csr.genblk1.csrm.MEPC_REGW);
|
||||
RequestDelayedMIP = 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -449,7 +529,7 @@ module testbench();
|
|||
ExpectedMemWriteDataW <= '0;
|
||||
ExpectedMemReadDataW <= '0;
|
||||
NumCSRW <= '0;
|
||||
end else begin
|
||||
end else if (dut.hart.ieu.c.InstrValidM) begin
|
||||
ExpectedPCW <= ExpectedPCM;
|
||||
ExpectedInstrW <= ExpectedInstrM;
|
||||
textW <= textM;
|
||||
|
|
@ -484,12 +564,6 @@ module testbench();
|
|||
// step2: make all checks in the write back stage.
|
||||
assign checkInstrW = InstrValidW & ~dut.hart.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction.
|
||||
always @(negedge clk) begin
|
||||
if(RequestDelayedMIP) begin
|
||||
$display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueW[NumCSRM]);
|
||||
MIPexpected = ExpectedCSRArrayValueW[NumCSRM];
|
||||
force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
|
||||
RequestDelayedMIP = 0;
|
||||
end
|
||||
// always check PC, instruction bits
|
||||
if (checkInstrW) begin
|
||||
InstrCountW += 1;
|
||||
|
|
@ -521,7 +595,7 @@ module testbench();
|
|||
if(MemOpW == "MemR" || MemOpW == "MemRW") begin
|
||||
if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW);
|
||||
`checkEQ("ReadDataW",dut.hart.ieu.dp.ReadDataW,ExpectedMemReadDataW)
|
||||
end else if(ExpectedTokens[MarkerIndex] == "MemW" || ExpectedTokens[MarkerIndex] == "MemRW") begin
|
||||
end else if(MemOpW == "MemW" || MemOpW == "MemRW") begin
|
||||
if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
|
||||
`checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW)
|
||||
end
|
||||
|
|
|
|||
|
|
@ -83,6 +83,7 @@ logic [3:0] dummy;
|
|||
"arch64priv": tests = arch64priv;
|
||||
"arch64c": if (`C_SUPPORTED) tests = arch64c;
|
||||
"arch64m": if (`M_SUPPORTED) tests = arch64m;
|
||||
"arch64d": if (`D_SUPPORTED) tests = arch64d;
|
||||
"imperas64i": tests = imperas64i;
|
||||
"imperas64p": tests = imperas64p;
|
||||
"imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu;
|
||||
|
|
@ -93,7 +94,9 @@ logic [3:0] dummy;
|
|||
"imperas64c": if (`C_SUPPORTED) tests = imperas64c;
|
||||
else tests = imperas64iNOc;
|
||||
"testsBP64": tests = testsBP64;
|
||||
// *** add arch f and d tests, peripheral tests
|
||||
"wally64i": tests = wally64i;
|
||||
"wally64priv": tests = wally64priv;
|
||||
"wally64periph": tests = wally64periph;
|
||||
endcase
|
||||
end else begin // RV32
|
||||
case (TEST)
|
||||
|
|
@ -110,51 +113,15 @@ logic [3:0] dummy;
|
|||
"imperas32a": if (`A_SUPPORTED) tests = imperas32a;
|
||||
"imperas32c": if (`C_SUPPORTED) tests = imperas32c;
|
||||
else tests = imperas32iNOc;
|
||||
// ***add arch f and d tests
|
||||
"wally32i": tests = wally32i;
|
||||
"wally32priv": tests = wally32priv;
|
||||
"wally32periph": tests = wally32periph;
|
||||
endcase
|
||||
end
|
||||
if (tests.size() == 1) begin
|
||||
$display("TEST %s not supported in this configuration", TEST);
|
||||
$stop;
|
||||
end
|
||||
//if (TEST == "arch-64m") //tests = {archtests64m};
|
||||
/* if (`XLEN == 64) begin // RV64
|
||||
if (`TESTSBP) begin
|
||||
tests = testsBP64;
|
||||
// testsbp should not run the other tests. It starts at address 0 rather than
|
||||
// 0x8000_0000, the next if must remain an else if.
|
||||
end else if (TESTSPERIPH)
|
||||
tests = imperastests64periph;
|
||||
else if (TESTSPRIV)
|
||||
tests = imperastests64p;
|
||||
else begin
|
||||
tests = {imperastests64p,imperastests64i, imperastests64periph};
|
||||
if (`C_SUPPORTED) tests = {tests, imperastests64ic};
|
||||
else tests = {tests, imperastests64iNOc};
|
||||
if (`F_SUPPORTED) tests = {imperastests64f, tests};
|
||||
if (`D_SUPPORTED) tests = {imperastests64d, tests};
|
||||
if (`MEM_VIRTMEM) tests = {imperastests64mmu, tests};
|
||||
if (`A_SUPPORTED) tests = {imperastests64a, tests};
|
||||
if (`M_SUPPORTED) tests = {imperastests64m, tests};
|
||||
end
|
||||
//tests = {imperastests64a, tests};
|
||||
end else begin // RV32
|
||||
// *** add the 32 bit bp tests
|
||||
if (TESTSPERIPH)
|
||||
tests = imperastests32periph;
|
||||
else if (TESTSPRIV)
|
||||
tests = imperastests32p;
|
||||
else begin
|
||||
tests = {archtests32i, imperastests32i, imperastests32p};//,imperastests32periph}; *** broken at the moment
|
||||
if (`C_SUPPORTED) tests = {tests, imperastests32ic};
|
||||
else tests = {tests, imperastests32iNOc};
|
||||
if (`F_SUPPORTED) tests = {imperastests32f, tests};
|
||||
if (`MEM_VIRTMEM) tests = {imperastests32mmu, tests};
|
||||
if (`A_SUPPORTED) tests = {imperastests32a, tests};
|
||||
if (`M_SUPPORTED) tests = {imperastests32m, tests};
|
||||
tests = {archtests32i};
|
||||
end
|
||||
end */
|
||||
end
|
||||
|
||||
string signame, memfilename, pathname;
|
||||
|
|
@ -202,9 +169,10 @@ logic [3:0] dummy;
|
|||
end
|
||||
end
|
||||
// read test vectors into memory
|
||||
if (tests[0] == `IMPERASTEST)
|
||||
pathname = tvpaths[tests[0].atoi()];
|
||||
/* if (tests[0] == `IMPERASTEST)
|
||||
pathname = tvpaths[0];
|
||||
else pathname = tvpaths[1];
|
||||
else pathname = tvpaths[1]; */
|
||||
memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||
$readmemh(memfilename, dut.uncore.dtim.RAM);
|
||||
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
|
||||
|
|
|
|||
|
|
@ -25,10 +25,12 @@
|
|||
|
||||
`define IMPERASTEST "0"
|
||||
`define RISCVARCHTEST "1"
|
||||
`define WALLYTEST "2"
|
||||
|
||||
string tvpaths[] = '{
|
||||
"../../tests/imperas-riscv-tests/work/",
|
||||
"../../addins/riscv-arch-test/work/"
|
||||
"../../addins/riscv-arch-test/work/",
|
||||
"../../tests/wally-riscv-arch-test/work/"
|
||||
};
|
||||
|
||||
string imperas32mmu[] = '{
|
||||
|
|
@ -636,6 +638,181 @@ string imperas32f[] = '{
|
|||
"rv64i_m/I/xori-01", "6010"
|
||||
};
|
||||
|
||||
|
||||
string arch64d[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv64i_m/D/d_fadd_b10-01", "8690",
|
||||
// "rv64i_m/D/d_fadd_b1-01", "8430",
|
||||
// "rv64i_m/D/d_fadd_b11-01", "74da0",
|
||||
// "rv64i_m/D/d_fadd_b12-01", "2350",
|
||||
// "rv64i_m/D/d_fadd_b13-01", "3cb0",
|
||||
// "rv64i_m/D/d_fadd_b2-01", "5160",
|
||||
// "rv64i_m/D/d_fadd_b3-01", "d640",
|
||||
// "rv64i_m/D/d_fadd_b4-01", "3900",
|
||||
// "rv64i_m/D/d_fadd_b5-01", "3d50",
|
||||
// "rv64i_m/D/d_fadd_b7-01", "5530",
|
||||
// "rv64i_m/D/d_fadd_b8-01", "11c10",
|
||||
"rv64i_m/D/d_fclass_b1-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.l_b25-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.l_b26-01", "2220",
|
||||
// "rv64i_m/D/d_fcvt.d.lu_b25-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.lu_b26-01", "2220",
|
||||
// "rv64i_m/D/d_fcvt.d.s_b1-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.s_b22-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.s_b23-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.s_b24-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.s_b27-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.s_b28-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.s_b29-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.w_b25-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.d.w_b26-01", "2220",
|
||||
// "rv64i_m/D/d_fcvt.d.wu_b25-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.wu_b26-01", "2220",
|
||||
// "rv64i_m/D/d_fcvt.l.d_b1-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.l.d_b22-01", "2260",
|
||||
// "rv64i_m/D/d_fcvt.l.d_b23-01", "2180",
|
||||
// "rv64i_m/D/d_fcvt.l.d_b24-01", "2360",
|
||||
// "rv64i_m/D/d_fcvt.l.d_b27-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.l.d_b28-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.l.d_b29-01", "22a0",
|
||||
// "rv64i_m/D/d_fcvt.lu.d_b1-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.lu.d_b22-01", "2260",
|
||||
// "rv64i_m/D/d_fcvt.lu.d_b23-01", "2180",
|
||||
// "rv64i_m/D/d_fcvt.lu.d_b24-01", "2360",
|
||||
// "rv64i_m/D/d_fcvt.lu.d_b27-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.lu.d_b28-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.lu.d_b29-01", "22a0",
|
||||
// "rv64i_m/D/d_fcvt.s.d_b1-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.s.d_b22-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.s.d_b23-01", "2180",
|
||||
// "rv64i_m/D/d_fcvt.s.d_b24-01", "2360",
|
||||
// "rv64i_m/D/d_fcvt.s.d_b27-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.s.d_b28-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.s.d_b29-01", "22a0",
|
||||
// "rv64i_m/D/d_fcvt.w.d_b1-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.w.d_b22-01", "2160",
|
||||
// "rv64i_m/D/d_fcvt.w.d_b23-01", "2180",
|
||||
// "rv64i_m/D/d_fcvt.w.d_b24-01", "2360",
|
||||
// "rv64i_m/D/d_fcvt.w.d_b27-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.w.d_b28-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.w.d_b29-01", "22a0",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b1-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b22-01", "2160",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b23-01", "2180",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b24-01", "2360",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b27-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b28-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b29-01", "22a0",
|
||||
// "rv64i_m/D/d_fdiv_b1-01", "8430",
|
||||
// "rv64i_m/D/d_fdiv_b20-01", "3fa0",
|
||||
// "rv64i_m/D/d_fdiv_b2-01", "5170",
|
||||
// "rv64i_m/D/d_fdiv_b21-01", "8a70",
|
||||
// "rv64i_m/D/d_fdiv_b3-01", "d630",
|
||||
// "rv64i_m/D/d_fdiv_b4-01", "38f0",
|
||||
// "rv64i_m/D/d_fdiv_b5-01", "3d50",
|
||||
// "rv64i_m/D/d_fdiv_b6-01", "38f0",
|
||||
// "rv64i_m/D/d_fdiv_b7-01", "5530",
|
||||
// "rv64i_m/D/d_fdiv_b8-01", "11c10",
|
||||
// "rv64i_m/D/d_fdiv_b9-01", "1b0f0",
|
||||
// "rv64i_m/D/d_feq_b1-01", "7430",
|
||||
// "rv64i_m/D/d_feq_b19-01", "c4c0",
|
||||
// "rv64i_m/D/d_fld-align-01", "2010",
|
||||
// "rv64i_m/D/d_fle_b1-01", "7430",
|
||||
// "rv64i_m/D/d_fle_b19-01", "c4c0",
|
||||
// "rv64i_m/D/d_flt_b1-01", "7430",
|
||||
// "rv64i_m/D/d_flt_b19-01", "d800",
|
||||
"rv64i_m/D/d_fmadd_b14-01", "3fd0",
|
||||
"rv64i_m/D/d_fmadd_b16-01", "43b0",
|
||||
"rv64i_m/D/d_fmadd_b17-01", "43b0",
|
||||
"rv64i_m/D/d_fmadd_b18-01", "5a20",
|
||||
"rv64i_m/D/d_fmadd_b2-01", "5ab0",
|
||||
"rv64i_m/D/d_fmadd_b3-01", "119d0",
|
||||
"rv64i_m/D/d_fmadd_b4-01", "3df0",
|
||||
"rv64i_m/D/d_fmadd_b5-01", "4480",
|
||||
"rv64i_m/D/d_fmadd_b6-01", "3df0",
|
||||
"rv64i_m/D/d_fmadd_b7-01", "6050",
|
||||
"rv64i_m/D/d_fmadd_b8-01", "15aa0",
|
||||
"rv64i_m/D/d_fmax_b1-01", "8430",
|
||||
"rv64i_m/D/d_fmax_b19-01", "d5c0",
|
||||
"rv64i_m/D/d_fmin_b1-01", "8430",
|
||||
"rv64i_m/D/d_fmin_b19-01", "d4b0",
|
||||
"rv64i_m/D/d_fmsub_b14-01", "3fd0",
|
||||
"rv64i_m/D/d_fmsub_b16-01", "43b0",
|
||||
"rv64i_m/D/d_fmsub_b17-01", "43b0",
|
||||
"rv64i_m/D/d_fmsub_b18-01", "5a20",
|
||||
"rv64i_m/D/d_fmsub_b2-01", "5ab0",
|
||||
"rv64i_m/D/d_fmsub_b3-01", "119f0",
|
||||
"rv64i_m/D/d_fmsub_b4-01", "3df0",
|
||||
"rv64i_m/D/d_fmsub_b5-01", "4480",
|
||||
"rv64i_m/D/d_fmsub_b6-01", "3df0",
|
||||
"rv64i_m/D/d_fmsub_b7-01", "6050",
|
||||
"rv64i_m/D/d_fmsub_b8-01", "15aa0",
|
||||
"rv64i_m/D/d_fmul_b1-01", "8430",
|
||||
"rv64i_m/D/d_fmul_b2-01", "5180",
|
||||
"rv64i_m/D/d_fmul_b3-01", "d640",
|
||||
"rv64i_m/D/d_fmul_b4-01", "38f0",
|
||||
"rv64i_m/D/d_fmul_b5-01", "3d50",
|
||||
"rv64i_m/D/d_fmul_b6-01", "38f0",
|
||||
"rv64i_m/D/d_fmul_b7-01", "5540",
|
||||
"rv64i_m/D/d_fmul_b8-01", "11c10",
|
||||
"rv64i_m/D/d_fmul_b9-01", "1b0f0",
|
||||
"rv64i_m/D/d_fmv.d.x_b25-01", "2110",
|
||||
"rv64i_m/D/d_fmv.d.x_b26-01", "2220",
|
||||
"rv64i_m/D/d_fmv.x.d_b1-01", "2120",
|
||||
"rv64i_m/D/d_fmv.x.d_b22-01", "2110",
|
||||
"rv64i_m/D/d_fmv.x.d_b23-01", "2110",
|
||||
"rv64i_m/D/d_fmv.x.d_b24-01", "2120",
|
||||
"rv64i_m/D/d_fmv.x.d_b27-01", "2120",
|
||||
"rv64i_m/D/d_fmv.x.d_b28-01", "2110",
|
||||
"rv64i_m/D/d_fmv.x.d_b29-01", "2120",
|
||||
"rv64i_m/D/d_fnmadd_b14-01", "3fd0",
|
||||
"rv64i_m/D/d_fnmadd_b16-01", "4390",
|
||||
"rv64i_m/D/d_fnmadd_b17-01", "4390",
|
||||
"rv64i_m/D/d_fnmadd_b18-01", "5a20",
|
||||
"rv64i_m/D/d_fnmadd_b2-01", "5ab0",
|
||||
"rv64i_m/D/d_fnmadd_b3-01", "119d0",
|
||||
"rv64i_m/D/d_fnmadd_b4-01", "3df0",
|
||||
"rv64i_m/D/d_fnmadd_b5-01", "4480",
|
||||
"rv64i_m/D/d_fnmadd_b6-01", "3df0",
|
||||
"rv64i_m/D/d_fnmadd_b7-01", "6050",
|
||||
"rv64i_m/D/d_fnmadd_b8-01", "15aa0",
|
||||
"rv64i_m/D/d_fnmsub_b14-01", "3fd0",
|
||||
"rv64i_m/D/d_fnmsub_b16-01", "4390",
|
||||
"rv64i_m/D/d_fnmsub_b17-01", "4390",
|
||||
"rv64i_m/D/d_fnmsub_b18-01", "5a20",
|
||||
"rv64i_m/D/d_fnmsub_b2-01", "5aa0",
|
||||
"rv64i_m/D/d_fnmsub_b3-01", "119d0",
|
||||
"rv64i_m/D/d_fnmsub_b4-01", "3e20",
|
||||
"rv64i_m/D/d_fnmsub_b5-01", "4480",
|
||||
"rv64i_m/D/d_fnmsub_b6-01", "3e10",
|
||||
"rv64i_m/D/d_fnmsub_b7-01", "6050",
|
||||
"rv64i_m/D/d_fnmsub_b8-01", "15aa0",
|
||||
"rv64i_m/D/d_fsd-align-01", "2010",
|
||||
"rv64i_m/D/d_fsgnj_b1-01", "8430",
|
||||
"rv64i_m/D/d_fsgnjn_b1-01", "8430",
|
||||
"rv64i_m/D/d_fsgnjx_b1-01", "8430",
|
||||
"rv64i_m/D/d_fsqrt_b1-01", "2110",
|
||||
"rv64i_m/D/d_fsqrt_b20-01", "3460",
|
||||
"rv64i_m/D/d_fsqrt_b2-01", "2190",
|
||||
"rv64i_m/D/d_fsqrt_b3-01", "2120",
|
||||
"rv64i_m/D/d_fsqrt_b4-01", "2110",
|
||||
"rv64i_m/D/d_fsqrt_b5-01", "2110",
|
||||
"rv64i_m/D/d_fsqrt_b7-01", "2110",
|
||||
"rv64i_m/D/d_fsqrt_b8-01", "2110",
|
||||
"rv64i_m/D/d_fsqrt_b9-01", "4c10",
|
||||
"rv64i_m/D/d_fsub_b10-01", "8660",
|
||||
"rv64i_m/D/d_fsub_b1-01", "8440",
|
||||
"rv64i_m/D/d_fsub_b11-01", "74da0",
|
||||
"rv64i_m/D/d_fsub_b12-01", "2350",
|
||||
"rv64i_m/D/d_fsub_b13-01", "3cb0",
|
||||
"rv64i_m/D/d_fsub_b2-01", "5160",
|
||||
"rv64i_m/D/d_fsub_b3-01", "d630",
|
||||
"rv64i_m/D/d_fsub_b4-01", "38f0",
|
||||
"rv64i_m/D/d_fsub_b5-01", "3d50",
|
||||
"rv64i_m/D/d_fsub_b7-01", "5530",
|
||||
"rv64i_m/D/d_fsub_b8-01", "11c10"
|
||||
};
|
||||
|
||||
string arch32priv[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv32i_m/privilege/ebreak", "2070",
|
||||
|
|
@ -669,7 +846,6 @@ string imperas32f[] = '{
|
|||
};
|
||||
|
||||
string arch32f[] = '{
|
||||
|
||||
`RISCVARCHTEST,
|
||||
// "rv32i_m/F/fadd_b1-01", "7220",
|
||||
// "rv32i_m/F/fadd_b10-01", "2270",
|
||||
|
|
@ -893,4 +1069,30 @@ string imperas32f[] = '{
|
|||
"rv32i_m/I/xori-01", "4010"
|
||||
};
|
||||
|
||||
string wally64i[] = '{
|
||||
`WALLYTEST,
|
||||
"rv64i_m/I/add-01", "9010",
|
||||
"rv64i_m/I/PIPELINE", "3010"
|
||||
};
|
||||
|
||||
string wally64priv[] = '{
|
||||
`WALLYTEST
|
||||
};
|
||||
|
||||
string wally64periph[] = '{
|
||||
`WALLYTEST
|
||||
};
|
||||
|
||||
string wally32i[] = '{
|
||||
`WALLYTEST,
|
||||
"rv32i_m/I/PIPELINE", "3010"
|
||||
};
|
||||
|
||||
string wally32priv[] = '{
|
||||
`WALLYTEST
|
||||
};
|
||||
|
||||
string wally32periph[] = '{
|
||||
`WALLYTEST
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue