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2
bin/CacheSim.py
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@ -5,7 +5,7 @@
## ##
## Written: lserafini@hmc.edu ## Written: lserafini@hmc.edu
## Created: 27 March 2023 ## Created: 27 March 2023
## Modified: 5 April 2023 ## Modified: 12 April 2023
## ##
## Purpose: Simulate a L1 D$ or I$ for comparison with Wally ## Purpose: Simulate a L1 D$ or I$ for comparison with Wally
## ##

29
docs/testplans/testplan.md Normal file
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@ -0,0 +1,29 @@
# CORE-V Wally Test Plan
CORE-V Wally is tested in the following ways:
* Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model.
* Run custom tests to cover virtual memory, PMP, privileged unit, and peripherals in lock step against ImperasDV.
* ***pending: Run random tests generated by risc-dv
* Run CoreMark and Embench benchmarks.
* Run performance validation against reference models for the branch predictor and caches.
* Run the TestFloat suite against all precisions of all operations for the FPU unit.
* *** 83.5% coverage of statements, branches, expressions, and FSM states and transitions
* Boot Buildroot Linux in lock-step against ImperasDV.
* Boot Buildroot Linux on an FPGA and run programs.
# Running Tests
#
# Detailed Test Plans
The test plans for specific units are lined below:
* Privileged Unit
* Memory Management Unit
* Peripherals
* Branch Predictor Performance Validation
* Cache Performance Validation
Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris.

18
sim/GetLineNum.do Normal file
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@ -0,0 +1,18 @@
# Alec Vercruysse
# 2023-04-12
# Note that the target string is regex, and needs to be double-escaped.
# e.g. to match a (, you need \\(.
proc GetLineNum {fname target} {
set f [open $fname]
set linectr 1
while {[gets $f line] != -1} {
if {[regexp $target $line]} {
close $f
return $linectr
}
incr linectr
}
close $f
return -code error \
"target string not found"
}

55
sim/coverage-exclusions-rv64gc.do
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@ -27,25 +27,56 @@
# This file should be a last resort. It's preferable to put # This file should be a last resort. It's preferable to put
# // coverage off # // coverage off
# statements inline with the code whenever possible. # statements inline with the code whenever possible.
# a hack to describe coverage exclusions without hardcoding linenumbers:
do GetLineNum.do
# LZA (i<64) statement confuses coverage tool # LZA (i<64) statement confuses coverage tool
# This is ugly to exlcude the whole file - is there a better option? // coverage off isn't working # This is ugly to exlcude the whole file - is there a better option? // coverage off isn't working
coverage exclude -srcfile lzc.sv coverage exclude -srcfile lzc.sv
# FDIVSQRT has
coverage exclude -scope /core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state DONE->BUSY
###################### ### Exclude D$ states and logic for the I$ instance
# Toggle exclusions # This is cleaner than trying to set an I$-specific pragma in cachefsm.sv (which would exclude it for the D$ instance too)
# Not used because toggle coverage isn't measured # Also exclude the write line to ready transition for the I$ since we can't get a flush during this operation.
###################### coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -fstate CurrState STATE_FLUSH STATE_FLUSH_WRITEBACK STATE_FLUSH_WRITEBACK STATE_WRITEBACK
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -ftrans CurrState STATE_WRITE_LINE->STATE_READY
# exclude unused transitions from case statement. Unfortunately the whole branch needs to be excluded I think. Expression coverage should still work.
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache state-case"] -item b 1
# exclude branch/condition coverage: LineDirty if statement
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FETCHStatement"] -item bc 1
# exclude the unreachable logic
set start [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-start: icache case"]
set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache case"]
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache WRITEBACKStatement"]
# exclude Atomic Operation logic
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache storeAMO"] -item e 1 -fecexprrow 6
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache storeAMO1"] -item e 1 -fecexprrow 2-4
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache AnyUpdateHit"] -item e 1 -fecexprrow 2
# cache write logic
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheW"] -item e 1 -fecexprrow 4
# output signal logic
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache StallStates"] -item e 1 -fecexprrow 8 12 14
set start [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-start: icache flushdirtycontrols"]
set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache flushdirtycontrols"]
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusW"]
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache SelAdrCauses"] -item e 1 -fecexprrow 4 10
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusRCauses"] -item e 1 -fecexprrow 1-2 12
# cache.sv AdrSelMux and CacheBusAdrMux, excluding unhit Flush branch
coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheBusAdrMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1 3
# CacheWay Dirty logic. -scope does not accept wildcards.
set numcacheways 4
for {set i 0} {$i < $numcacheways} {incr i} {
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6
# below: flushD can't go high during an icache write b/c of pipeline stall
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetValidEN"] -item e 1 -fecexprrow 4
}
# Exclude DivBusyE from all design units because rv64gc uses the fdivsqrt unit for integer division
#coverage exclude -togglenode DivBusyE -du *
# Exclude QuotM and RemM from MDU because rv64gc uses the fdivsqrt rather tha div unit for integer division
#coverage exclude -togglenode /dut/core/mdu/mdu/QuotM
#coverage exclude -togglenode /dut/core/mdu/mdu/RemM
# StallFCause is hardwired to 0
#coverage exclude -togglenode /dut/core/hzu/StallFCause
# Excluding peripherals as sources of instructions for the ifu # Excluding peripherals as sources of instructions for the ifu
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/clintdec coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/clintdec

2
sim/rv64gc_CacheSim.py
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@ -1,7 +1,7 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
########################################### ###########################################
## CacheSimTest.py ## rv64gc_CacheSim.py
## ##
## Written: lserafini@hmc.edu ## Written: lserafini@hmc.edu
## Created: 11 April 2023 ## Created: 11 April 2023

20
src/cache/cache.sv vendored
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@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// cache // cache.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Ross Thompson ross1728@gmail.com
// Created: 7 July 2021 // Created: 7 July 2021
@ -122,7 +122,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
// Select victim way for associative caches // Select victim way for associative caches
if(NUMWAYS > 1) begin:vict if(NUMWAYS > 1) begin:vict
cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU( cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU(
.clk, .reset, .CacheEn, .FlushStage, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn, .clk, .reset, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn,
.SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache); .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache);
end else end else
assign VictimWay = 1'b1; // one hot. assign VictimWay = 1'b1; // one hot.
@ -167,22 +167,22 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
// Adjust byte mask from word to cache line // Adjust byte mask from word to cache line
onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded)); onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded));
for(index = 0; index < 2**LOGCWPL; index++) begin for(index = 0; index < 2**LOGCWPL; index++) begin
assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0; assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
end end
assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1. assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1.
// Merge write data into fetched cache line for store miss // Merge write data into fetched cache line for store miss
for(index = 0; index < LINELEN/8; index++) begin for(index = 0; index < LINELEN/8; index++) begin
mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]), mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
.d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index])); .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index]));
end end
assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0; assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0;
end end
else else
begin:WriteSelLogic begin:WriteSelLogic
// No need for this mux if the cache does not handle writes. // No need for this mux if the cache does not handle writes.
assign LineWriteData = FetchBuffer; assign LineWriteData = FetchBuffer;
assign LineByteMask = '1; assign LineByteMask = '1;
end end
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Flush logic // Flush logic
@ -203,8 +203,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
assign FlushWayFlag = FlushWay[NUMWAYS-1]; assign FlushWayFlag = FlushWay[NUMWAYS-1];
end // block: flushlogic end // block: flushlogic
else begin:flushlogic else begin:flushlogic
assign FlushWayFlag = 0; assign FlushWayFlag = 0;
assign FlushAdrFlag = 0; assign FlushAdrFlag = 0;
end end
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////

53
src/cache/cacheLRU.sv vendored
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@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// dcache (data cache) // cacheLRU.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Ross Thompson ross1728@gmail.com
// Created: 20 July 2021 // Created: 20 July 2021
@ -32,12 +32,11 @@
module cacheLRU module cacheLRU
#(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128) ( #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128) (
input logic clk, input logic clk,
input logic reset, input logic reset,
input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations)
input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant
input logic [NUMWAYS-1:0] HitWay, // Which way is valid and matches PAdr's tag input logic [NUMWAYS-1:0] HitWay, // Which way is valid and matches PAdr's tag
input logic [NUMWAYS-1:0] ValidWay, // Which ways for a particular set are valid, ignores tag input logic [NUMWAYS-1:0] ValidWay, // Which ways for a particular set are valid, ignores tag
input logic [SETLEN-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr input logic [SETLEN-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
input logic [SETLEN-1:0] PAdr, // Physical address input logic [SETLEN-1:0] PAdr, // Physical address
input logic LRUWriteEn, // Update the LRU state input logic LRUWriteEn, // Update the LRU state
input logic SetValid, // Set the dirty bit in the selected way and set input logic SetValid, // Set the dirty bit in the selected way and set
@ -90,16 +89,26 @@ module cacheLRU
assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{WayEncoded[row]}}; assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{WayEncoded[row]}};
end end
genvar r, a, s; genvar node;
assign LRUUpdate[NUMWAYS-2] = '1; assign LRUUpdate[NUMWAYS-2] = '1;
for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin : enables for(node = NUMWAYS-2; node >= NUMWAYS/2; node--) begin : enables
localparam p = NUMWAYS - s - 1; localparam ctr = NUMWAYS - node - 1;
localparam g = log2(p); localparam ctr_depth = log2(ctr);
localparam t0 = s - p; localparam lchild = node - ctr;
localparam t1 = t0 - 1; localparam rchild = lchild - 1;
localparam r = LOGNUMWAYS - g; localparam r = LOGNUMWAYS - ctr_depth;
assign LRUUpdate[t0] = LRUUpdate[s] & ~WayEncoded[r];
assign LRUUpdate[t1] = LRUUpdate[s] & WayEncoded[r]; // the child node will be updated if its parent was updated and
// the WayEncoded bit was the correct value.
// The if statement is only there for coverage since LRUUpdate[root] is always 1.
if (node == NUMWAYS-2) begin
assign LRUUpdate[lchild] = ~WayEncoded[r];
assign LRUUpdate[rchild] = WayEncoded[r];
end
else begin
assign LRUUpdate[lchild] = LRUUpdate[node] & ~WayEncoded[r];
assign LRUUpdate[rchild] = LRUUpdate[node] & WayEncoded[r];
end
end end
// The root node of the LRU tree will always be selected in LRUUpdate. No mux needed. // The root node of the LRU tree will always be selected in LRUUpdate. No mux needed.
@ -107,15 +116,15 @@ module cacheLRU
mux2 #(1) LRUMuxes[NUMWAYS-3:0](CurrLRU[NUMWAYS-3:0], ~WayExpanded[NUMWAYS-3:0], LRUUpdate[NUMWAYS-3:0], NextLRU[NUMWAYS-3:0]); mux2 #(1) LRUMuxes[NUMWAYS-3:0](CurrLRU[NUMWAYS-3:0], ~WayExpanded[NUMWAYS-3:0], LRUUpdate[NUMWAYS-3:0], NextLRU[NUMWAYS-3:0]);
// Compute next victim way. // Compute next victim way.
for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin for(node = NUMWAYS-2; node >= NUMWAYS/2; node--) begin
localparam t0 = 2*s - NUMWAYS; localparam t0 = 2*node - NUMWAYS;
localparam t1 = t0 + 1; localparam t1 = t0 + 1;
assign Intermediate[s] = CurrLRU[s] ? Intermediate[t0] : Intermediate[t1]; assign Intermediate[node] = CurrLRU[node] ? Intermediate[t0] : Intermediate[t1];
end end
for(s = NUMWAYS/2-1; s >= 0; s--) begin for(node = NUMWAYS/2-1; node >= 0; node--) begin
localparam int0 = (NUMWAYS/2-1-s)*2; localparam int0 = (NUMWAYS/2-1-node)*2;
localparam int1 = int0 + 1; localparam int1 = int0 + 1;
assign Intermediate[s] = CurrLRU[s] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0]; assign Intermediate[node] = CurrLRU[node] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0];
end end
logic [NUMWAYS-1:0] FirstZero; logic [NUMWAYS-1:0] FirstZero;
@ -134,11 +143,9 @@ module cacheLRU
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
if(CacheEn) begin if(CacheEn) begin
// if((InvalidateCache | FlushCache) & ~FlushStage) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; if(LRUWriteEn)
if (LRUWriteEn & ~FlushStage) begin
LRUMemory[PAdr] <= NextLRU; LRUMemory[PAdr] <= NextLRU;
end if(LRUWriteEn & (PAdr == CacheSet))
if(LRUWriteEn & ~FlushStage & (PAdr == CacheSet))
CurrLRU <= #1 NextLRU; CurrLRU <= #1 NextLRU;
else else
CurrLRU <= #1 LRUMemory[CacheSet]; CurrLRU <= #1 LRUMemory[CacheSet];

46
src/cache/cachefsm.sv vendored
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@ -1,11 +1,11 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// dcache (data cache) fsm // cachefsm.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Ross Thompson ross1728@gmail.com
// Created: 25 August 2021 // Created: 25 August 2021
// Modified: 20 January 2023 // Modified: 20 January 2023
// //
// Purpose: Controller for the dcache fsm // Purpose: Controller for the cache fsm
// //
// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1) // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1)
// //
@ -47,7 +47,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
output logic [1:0] CacheBusRW, // [1] Read (cache line fetch) or [0] write bus (cache line writeback) output logic [1:0] CacheBusRW, // [1] Read (cache line fetch) or [0] write bus (cache line writeback)
// performance counter outputs // performance counter outputs
output logic CacheMiss, // Cache miss output logic CacheMiss, // Cache miss
output logic CacheAccess, // Cache access output logic CacheAccess, // Cache access
// cache internals // cache internals
input logic CacheHit, // Exactly 1 way hits input logic CacheHit, // Exactly 1 way hits
@ -55,7 +55,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
input logic FlushAdrFlag, // On last set of a cache flush input logic FlushAdrFlag, // On last set of a cache flush
input logic FlushWayFlag, // On the last way for any set of a cache flush input logic FlushWayFlag, // On the last way for any set of a cache flush
output logic SelAdr, // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr output logic SelAdr, // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr
output logic SetValid, // Set the dirty bit in the selected way and set output logic SetValid, // Set the valid bit in the selected way and set
output logic ClearDirty, // Clear the dirty bit in the selected way and set output logic ClearDirty, // Clear the dirty bit in the selected way and set
output logic SetDirty, // Set the dirty bit in the selected way and set output logic SetDirty, // Set the dirty bit in the selected way and set
output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback
@ -89,13 +89,13 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
assign AMO = CacheAtomic[1] & (&CacheRW); assign AMO = CacheAtomic[1] & (&CacheRW);
assign StoreAMO = AMO | CacheRW[0]; assign StoreAMO = AMO | CacheRW[0];
assign AnyMiss = (StoreAMO | CacheRW[1]) & ~CacheHit & ~InvalidateCache; assign AnyMiss = (StoreAMO | CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: icache storeAMO
assign AnyUpdateHit = (StoreAMO) & CacheHit; assign AnyUpdateHit = (StoreAMO) & CacheHit; // exclusion-tag: icache storeAMO1
assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit); assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit); // exclusion-tag: icache AnyUpdateHit
assign FlushFlag = FlushAdrFlag & FlushWayFlag; assign FlushFlag = FlushAdrFlag & FlushWayFlag;
// outputs for the performance counters. // outputs for the performance counters.
assign CacheAccess = (AMO | CacheRW[1] | CacheRW[0]) & CurrState == STATE_READY; assign CacheAccess = (AMO | CacheRW[1] | CacheRW[0]) & CurrState == STATE_READY; // exclusion-tag: icache CacheW
assign CacheMiss = CacheAccess & ~CacheHit; assign CacheMiss = CacheAccess & ~CacheHit;
// special case on reset. When the fsm first exists reset the // special case on reset. When the fsm first exists reset the
@ -109,17 +109,18 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
always_comb begin always_comb begin
NextState = STATE_READY; NextState = STATE_READY;
case (CurrState) case (CurrState) // exclusion-tag: icache state-case
STATE_READY: if(InvalidateCache) NextState = STATE_READY; STATE_READY: if(InvalidateCache) NextState = STATE_READY;
else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH;
else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; // exclusion-tag: icache FETCHStatement
else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK; else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement
else NextState = STATE_READY; else NextState = STATE_READY;
STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE;
else NextState = STATE_FETCH; else NextState = STATE_FETCH;
STATE_WRITE_LINE: NextState = STATE_READ_HOLD; STATE_WRITE_LINE: NextState = STATE_READ_HOLD;
STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD;
else NextState = STATE_READY; else NextState = STATE_READY;
// exclusion-tag-start: icache case
STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH; STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH;
else NextState = STATE_WRITEBACK; else NextState = STATE_WRITEBACK;
// eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
@ -129,13 +130,14 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH; STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH;
else if(CacheBusAck) NextState = STATE_READ_HOLD; else if(CacheBusAck) NextState = STATE_READ_HOLD;
else NextState = STATE_FLUSH_WRITEBACK; else NextState = STATE_FLUSH_WRITEBACK;
// exclusion-tag-end: icache case
default: NextState = STATE_READY; default: NextState = STATE_READY;
endcase endcase
end end
// com back to CPU // com back to CPU
assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & CurrState == STATE_READ_HOLD); assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & CurrState == STATE_READ_HOLD);
assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | // exclusion-tag: icache StallStates
(CurrState == STATE_FETCH) | (CurrState == STATE_FETCH) |
(CurrState == STATE_WRITEBACK) | (CurrState == STATE_WRITEBACK) |
(CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. (CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
@ -143,12 +145,14 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
(CurrState == STATE_FLUSH_WRITEBACK); (CurrState == STATE_FLUSH_WRITEBACK);
// write enables internal to cache // write enables internal to cache
assign SetValid = CurrState == STATE_WRITE_LINE; assign SetValid = CurrState == STATE_WRITE_LINE;
assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) | // coverage off -item e 1 -fecexprrow 8
(CurrState == STATE_WRITE_LINE & (StoreAMO));
assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(StoreAMO)) |
(CurrState == STATE_FLUSH & LineDirty); // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set.
assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) | assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) |
(CurrState == STATE_WRITE_LINE); (CurrState == STATE_WRITE_LINE) & ~FlushStage;
// exclusion-tag-start: icache flushdirtycontrols
assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) | // exclusion-tag: icache SetDirty
(CurrState == STATE_WRITE_LINE & (StoreAMO));
assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(StoreAMO)) | // exclusion-tag: icache ClearDirty
(CurrState == STATE_FLUSH & LineDirty); // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set.
// Flush and eviction controls // Flush and eviction controls
assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) | assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
(CurrState == STATE_READY & AnyMiss & LineDirty); (CurrState == STATE_READY & AnyMiss & LineDirty);
@ -162,20 +166,20 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
(CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck); (CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck);
assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) | assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) |
(CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck); (CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck);
// exclusion-tag-end: icache flushdirtycontrols
// Bus interface controls // Bus interface controls
assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | // exclusion-tag: icache CacheBusRCauses
(CurrState == STATE_FETCH & ~CacheBusAck) | (CurrState == STATE_FETCH & ~CacheBusAck) |
(CurrState == STATE_WRITEBACK & CacheBusAck); (CurrState == STATE_WRITEBACK & CacheBusAck);
assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) | assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) | // exclusion-tag: icache CacheBusW
(CurrState == STATE_WRITEBACK & ~CacheBusAck) | (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
(CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck); (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck);
assign SelAdr = (CurrState == STATE_READY & (StoreAMO | AnyMiss)) | // changes if store delay hazard removed assign SelAdr = (CurrState == STATE_READY & (StoreAMO | AnyMiss)) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed
(CurrState == STATE_FETCH) | (CurrState == STATE_FETCH) |
(CurrState == STATE_WRITEBACK) | (CurrState == STATE_WRITEBACK) |
(CurrState == STATE_WRITE_LINE) | (CurrState == STATE_WRITE_LINE) |
resetDelay; resetDelay;
assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD; assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD;
assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache; assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache;

17
src/cache/cacheway.sv vendored
View file

@ -35,7 +35,7 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
input logic reset, input logic reset,
input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations) input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations)
input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant
input logic [$clog2(NUMLINES)-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr input logic [$clog2(NUMLINES)-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
input logic [`PA_BITS-1:0] PAdr, // Physical address input logic [`PA_BITS-1:0] PAdr, // Physical address
input logic [LINELEN-1:0] LineWriteData, // Final data written to cache (D$ only) input logic [LINELEN-1:0] LineWriteData, // Final data written to cache (D$ only)
input logic SetValid, // Set the valid bit in the selected way and set input logic SetValid, // Set the valid bit in the selected way and set
@ -45,14 +45,14 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
input logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr input logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
input logic VictimWay, // LRU selected this way as victim to evict input logic VictimWay, // LRU selected this way as victim to evict
input logic FlushWay, // This way is selected for flush and possible writeback if dirty input logic FlushWay, // This way is selected for flush and possible writeback if dirty
input logic InvalidateCache,//Clear all valid bits input logic InvalidateCache,// Clear all valid bits
input logic [LINELEN/8-1:0] LineByteMask, // Final byte enables to cache (D$ only) input logic [LINELEN/8-1:0] LineByteMask, // Final byte enables to cache (D$ only)
output logic [LINELEN-1:0] ReadDataLineWay,// This way's read data if valid output logic [LINELEN-1:0] ReadDataLineWay,// This way's read data if valid
output logic HitWay, // This way hits output logic HitWay, // This way hits
output logic ValidWay, // This way is valid output logic ValidWay, // This way is valid
output logic DirtyWay, // This way is dirty output logic DirtyWay, // This way is dirty
output logic [TAGLEN-1:0] TagWay); // THis way's tag if valid output logic [TAGLEN-1:0] TagWay); // This way's tag if valid
localparam WORDSPERLINE = LINELEN/`XLEN; localparam WORDSPERLINE = LINELEN/`XLEN;
localparam BYTESPERLINE = LINELEN/8; localparam BYTESPERLINE = LINELEN/8;
@ -97,18 +97,13 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
assign SetValidWay = SetValid & SelData; assign SetValidWay = SetValid & SelData;
assign SetDirtyWay = SetDirty & SelData; // exclusion-tag: icache SetDirtyWay
assign ClearDirtyWay = ClearDirty & SelData; assign ClearDirtyWay = ClearDirty & SelData;
if (!READ_ONLY_CACHE) begin assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn
assign SetDirtyWay = SetDirty & SelData; assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: icache SetValidEN
assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage;
end
else begin
assign SelectedWriteWordEn = SetValidWay & ~FlushStage;
end
// If writing the whole line set all write enables to 1, else only set the correct word. // If writing the whole line set all write enables to 1, else only set the correct word.
assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR
assign SetValidEN = SetValidWay & ~FlushStage;
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Tag Array // Tag Array

5
src/cache/subcachelineread.sv vendored
View file

@ -1,11 +1,11 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// subcachelineread // subcachelineread.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Ross Thompson ross1728@gmail.com
// Created: 4 February 2022 // Created: 4 February 2022
// Modified: 20 January 2023 // Modified: 20 January 2023
// //
// Purpose: Muxes the cache line downto the word size. Also include possilbe save/restore registers/muxes. // Purpose: Muxes the cache line down to the word size. Also include possible save/restore registers/muxes.
// //
// Documentation: RISC-V System on Chip Design Chapter 7 // Documentation: RISC-V System on Chip Design Chapter 7
@ -31,7 +31,6 @@
module subcachelineread #(parameter LINELEN, WORDLEN, module subcachelineread #(parameter LINELEN, WORDLEN,
parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$ parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$
input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address
input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline
output logic [WORDLEN-1:0] ReadDataWord // read data of selected word. output logic [WORDLEN-1:0] ReadDataWord // read data of selected word.

28
src/ebu/ahbcacheinterface.sv
View file

@ -38,27 +38,27 @@ module ahbcacheinterface #(
)( )(
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
// bus interface controls // bus interface controls
input logic HREADY, // AHB peripheral ready input logic HREADY, // AHB peripheral ready
output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
output logic HWRITE, // AHB 0: Read operation 1: Write operation output logic HWRITE, // AHB 0: Read operation 1: Write operation
output logic [2:0] HSIZE, // AHB transaction width output logic [2:0] HSIZE, // AHB transaction width
output logic [2:0] HBURST, // AHB burst length output logic [2:0] HBURST, // AHB burst length
// bus interface buses // bus interface buses
input logic [`AHBW-1:0] HRDATA, // AHB read data input logic [`AHBW-1:0] HRDATA, // AHB read data
output logic [`PA_BITS-1:0] HADDR, // AHB address output logic [`PA_BITS-1:0] HADDR, // AHB address
output logic [`AHBW-1:0] HWDATA, // AHB write data output logic [`AHBW-1:0] HWDATA, // AHB write data
output logic [`AHBW/8-1:0] HWSTRB, // AHB byte mask output logic [`AHBW/8-1:0] HWSTRB, // AHB byte mask
// cache interface // cache interface
input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line
input logic [`LLEN-1:0] CacheReadDataWordM, // one word of cache line during a writeback input logic [`LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback
input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$
input logic Cacheable, // Memory operation is cachable input logic Cacheable, // Memory operation is cachable
input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
output logic CacheBusAck, // Handshack to $ indicating bus transaction completed output logic CacheBusAck, // Handshake to $ indicating bus transaction completed
output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus
output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase
output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
// uncached interface // uncached interface
input logic [`PA_BITS-1:0] PAdr, // Physical address of uncached memory operation input logic [`PA_BITS-1:0] PAdr, // Physical address of uncached memory operation
@ -77,7 +77,7 @@ module ahbcacheinterface #(
logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage
logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA
logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data
genvar index; genvar index;
@ -107,7 +107,7 @@ module ahbcacheinterface #(
end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0]; end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0];
mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]), mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]),
.s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
// *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
@ -119,5 +119,5 @@ module ahbcacheinterface #(
buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm( buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm(
.HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
.CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed, .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed,
.HREADY, .HTRANS, .HWRITE, .HBURST); .HREADY, .HTRANS, .HWRITE, .HBURST);
endmodule endmodule

16
src/ebu/ahbinterface.sv
View file

@ -32,21 +32,21 @@
module ahbinterface #( module ahbinterface #(
parameter LSU = 0 // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits parameter LSU = 0 // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits
)( )(
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
// bus interface // bus interface
input logic HREADY, // AHB peripheral ready input logic HREADY, // AHB peripheral ready
output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
output logic HWRITE, // AHB 0: Read operation 1: Write operation output logic HWRITE, // AHB 0: Read operation 1: Write operation
input logic [`XLEN-1:0] HRDATA, // AHB read data input logic [`XLEN-1:0] HRDATA, // AHB read data
output logic [`XLEN-1:0] HWDATA, // AHB write data output logic [`XLEN-1:0] HWDATA, // AHB write data
output logic [`XLEN/8-1:0] HWSTRB, // AHB byte mask output logic [`XLEN/8-1:0] HWSTRB, // AHB byte mask
// lsu/ifu interface // lsu/ifu interface
input logic Stall, // Core pipeline is stalled input logic Stall, // Core pipeline is stalled
input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write
input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word
input logic [`XLEN-1:0] WriteData, // IEU write data for a store input logic [`XLEN-1:0] WriteData, // IEU write data for a store
output logic BusStall, // Bus is busy with an in flight memory operation output logic BusStall, // Bus is busy with an in flight memory operation
output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer // Register to hold HRDATA after arriving from the bus output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer // Register to hold HRDATA after arriving from the bus

30
src/ebu/buscachefsm.sv
View file

@ -40,29 +40,29 @@ module buscachefsm #(
input logic HRESETn, input logic HRESETn,
// IEU interface // IEU interface
input logic Stall, // Core pipeline is stalled input logic Stall, // Core pipeline is stalled
input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write
output logic BusStall, // Bus is busy with an in flight memory operation output logic BusStall, // Bus is busy with an in flight memory operation
output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
// ahb cache interface locals. // ahb cache interface locals.
output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA
// cache interface // cache interface
input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
output logic CacheBusAck, // Handshack to $ indicating bus transaction completed output logic CacheBusAck, // Handshack to $ indicating bus transaction completed
// lsu interface // lsu interface
output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase
output logic [AHBWLOGBWPL-1:0] BeatCountDelayed, // Beat within the cache line in the second (Data) cache stage output logic [AHBWLOGBWPL-1:0] BeatCountDelayed, // Beat within the cache line in the second (Data) cache stage
output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
// BUS interface // BUS interface
input logic HREADY, // AHB peripheral ready input logic HREADY, // AHB peripheral ready
output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
output logic HWRITE, // AHB 0: Read operation 1: Write operation output logic HWRITE, // AHB 0: Read operation 1: Write operation
output logic [2:0] HBURST // AHB burst length output logic [2:0] HBURST // AHB burst length
); );
typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype; typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype;
@ -78,8 +78,8 @@ module buscachefsm #(
logic CacheAccess; logic CacheAccess;
always_ff @(posedge HCLK) always_ff @(posedge HCLK)
if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE;
else CurrState <= #1 NextState; else CurrState <= #1 NextState;
always_comb begin always_comb begin
case(CurrState) case(CurrState)

36
src/ebu/controllerinput.sv
View file

@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// controller input stage // controllerinput.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Ross Thompson ross1728@gmail.com
// Created: August 31, 2022 // Created: August 31, 2022
@ -36,26 +36,26 @@
module controllerinput #( module controllerinput #(
parameter SAVE_ENABLED = 1 // 1: Save manager inputs if Save = 1, 0: Don't save inputs parameter SAVE_ENABLED = 1 // 1: Save manager inputs if Save = 1, 0: Don't save inputs
)( )(
input logic HCLK, input logic HCLK,
input logic HRESETn, input logic HRESETn,
input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs
input logic Restore, // Restore a saved manager inputs when it is finally granted input logic Restore, // Restore a saved manager inputs when it is finally granted
input logic Disable, // Supress HREADY to the non-granted manager input logic Disable, // Suppress HREADY to the non-granted manager
output logic Request, // This manager is making a request output logic Request, // This manager is making a request
// controller input // controller input
input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation
input logic [2:0] HSIZEIn, // Manager input. AHB transaction width input logic [2:0] HSIZEIn, // Manager input. AHB transaction width
input logic [2:0] HBURSTIn, // Manager input. AHB burst length input logic [2:0] HBURSTIn, // Manager input. AHB burst length
input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address
output logic HREADYOut, // Indicate to manager the peripherial is not busy and another manager does not have priority output logic HREADYOut, // Indicate to manager the peripheral is not busy and another manager does not have priority
// controller output // controller output
output logic [1:0] HTRANSOut, // Aribrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ output logic [1:0] HTRANSOut, // Arbitrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
output logic HWRITEOut, // Aribrated manager transaction. AHB 0: Read operation 1: Write operation output logic HWRITEOut, // Arbitrated manager transaction. AHB 0: Read operation 1: Write operation
output logic [2:0] HSIZEOut, // Aribrated manager transaction. AHB transaction width output logic [2:0] HSIZEOut, // Arbitrated manager transaction. AHB transaction width
output logic [2:0] HBURSTOut, // Aribrated manager transaction. AHB burst length output logic [2:0] HBURSTOut, // Arbitrated manager transaction. AHB burst length
output logic [`PA_BITS-1:0] HADDROut, // Aribrated manager transaction. AHB address output logic [`PA_BITS-1:0] HADDROut, // Arbitrated manager transaction. AHB address
input logic HREADYIn // Peripherial ready input logic HREADYIn // Peripheral ready
); );
logic HWRITESave; logic HWRITESave;

6
src/ebu/ebufsmarb.sv
View file

@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// ebufsmarb // ebufsmarb.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Ross Thompson ross1728@gmail.com
// Created: 23 January 2023 // Created: 23 January 2023
@ -55,7 +55,7 @@ module ebufsmarb (
logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration
logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst
logic BeatCntEn; logic BeatCntEn;
logic [3:0] BeatCount; // Position within a burst transfer logic [3:0] BeatCount; // Position within a burst transfer
logic BeatCntReset; logic BeatCntReset;
logic [3:0] Threshold; // Number of beats derived from HBURST logic [3:0] Threshold; // Number of beats derived from HBURST
@ -86,7 +86,7 @@ module ebufsmarb (
// Controller 1 (LSU) // Controller 1 (LSU)
// When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state. // When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state.
// Once the LSU request is done the fsm returns to IDLE. To prevent the LSU from regaining // Once the LSU request is done the fsm returns to IDLE. To prevent the LSU from regaining
// priority and re issuing the same memroy operation, the delayed IFUReqD squashes the LSU request. // priority and re-issuing the same memory operation, the delayed IFUReqD squashes the LSU request.
// This is necessary because the pipeline is stalled for the entire duration of both transactions, // This is necessary because the pipeline is stalled for the entire duration of both transactions,
// and the LSU memory request will stil be active. // and the LSU memory request will stil be active.
flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD); flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD);

22
src/fpu/fcmp.sv
View file

@ -71,11 +71,11 @@ module fcmp (
// EQ - quiet - sets invalid if signaling NaN input // EQ - quiet - sets invalid if signaling NaN input
always_comb begin always_comb begin
case (OpCtrl[2:0]) case (OpCtrl[2:0])
3'b110: CmpNV = EitherSNaN;//min 3'b110: CmpNV = EitherSNaN; //min
3'b101: CmpNV = EitherSNaN;//max 3'b101: CmpNV = EitherSNaN; //max
3'b010: CmpNV = EitherSNaN;//equal 3'b010: CmpNV = EitherSNaN; //equal
3'b001: CmpNV = EitherNaN;//less than 3'b001: CmpNV = EitherNaN; //less than
3'b011: CmpNV = EitherNaN;//less than or equal 3'b011: CmpNV = EitherNaN; //less than or equal
default: CmpNV = 1'bx; default: CmpNV = 1'bx;
endcase endcase
end end
@ -137,19 +137,19 @@ module fcmp (
if(YNaN) CmpFpRes = NaNRes; // X = NaN Y = NaN if(YNaN) CmpFpRes = NaNRes; // X = NaN Y = NaN
else CmpFpRes = Y; // X = NaN Y != NaN else CmpFpRes = Y; // X = NaN Y != NaN
else else
if(YNaN) CmpFpRes = X; // X != NaN Y = NaN if(YNaN) CmpFpRes = X; // X != NaN Y = NaN
else // X,Y != NaN else // X,Y != NaN
if(LT) CmpFpRes = Y; // X < Y if(LT) CmpFpRes = Y; // X < Y
else CmpFpRes = X; // X > Y else CmpFpRes = X; // X > Y
else // MIN else // MIN
if(XNaN) if(XNaN)
if(YNaN) CmpFpRes = NaNRes; // X = NaN Y = NaN if(YNaN) CmpFpRes = NaNRes; // X = NaN Y = NaN
else CmpFpRes = Y; // X = NaN Y != NaN else CmpFpRes = Y; // X = NaN Y != NaN
else else
if(YNaN) CmpFpRes = X; // X != NaN Y = NaN if(YNaN) CmpFpRes = X; // X != NaN Y = NaN
else // X,Y != NaN else // X,Y != NaN
if(LT) CmpFpRes = X; // X < Y if(LT) CmpFpRes = X; // X < Y
else CmpFpRes = Y; // X > Y else CmpFpRes = Y; // X > Y
// LT/LE/EQ // LT/LE/EQ
// - -0 = 0 // - -0 = 0

44
src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
View file

@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// fdivsqrtpreproc.sv // fdivsqrtexpcalc.sv
// //
// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
// Modified:13 January 2022 // Modified:13 January 2022
@ -30,11 +30,11 @@
module fdivsqrtexpcalc( module fdivsqrtexpcalc(
input logic [`FMTBITS-1:0] Fmt, input logic [`FMTBITS-1:0] Fmt,
input logic [`NE-1:0] Xe, Ye, input logic [`NE-1:0] Xe, Ye,
input logic Sqrt, input logic Sqrt,
input logic XZero, input logic XZero,
input logic [`DIVBLEN:0] ell, m, input logic [`DIVBLEN:0] ell, m,
output logic [`NE+1:0] Qe output logic [`NE+1:0] Qe
); );
logic [`NE-2:0] Bias; logic [`NE-2:0] Bias;
logic [`NE+1:0] SXExp; logic [`NE+1:0] SXExp;
@ -42,28 +42,28 @@ module fdivsqrtexpcalc(
logic [`NE+1:0] DExp; logic [`NE+1:0] DExp;
if (`FPSIZES == 1) begin if (`FPSIZES == 1) begin
assign Bias = (`NE-1)'(`BIAS); assign Bias = (`NE-1)'(`BIAS);
end else if (`FPSIZES == 2) begin end else if (`FPSIZES == 2) begin
assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1);
end else if (`FPSIZES == 3) begin end else if (`FPSIZES == 3) begin
always_comb always_comb
case (Fmt) case (Fmt)
`FMT: Bias = (`NE-1)'(`BIAS); `FMT: Bias = (`NE-1)'(`BIAS);
`FMT1: Bias = (`NE-1)'(`BIAS1); `FMT1: Bias = (`NE-1)'(`BIAS1);
`FMT2: Bias = (`NE-1)'(`BIAS2); `FMT2: Bias = (`NE-1)'(`BIAS2);
default: Bias = 'x; default: Bias = 'x;
endcase endcase
end else if (`FPSIZES == 4) begin end else if (`FPSIZES == 4) begin
always_comb always_comb
case (Fmt) case (Fmt)
2'h3: Bias = (`NE-1)'(`Q_BIAS); 2'h3: Bias = (`NE-1)'(`Q_BIAS);
2'h1: Bias = (`NE-1)'(`D_BIAS); 2'h1: Bias = (`NE-1)'(`D_BIAS);
2'h0: Bias = (`NE-1)'(`S_BIAS); 2'h0: Bias = (`NE-1)'(`S_BIAS);
2'h2: Bias = (`NE-1)'(`H_BIAS); 2'h2: Bias = (`NE-1)'(`H_BIAS);
endcase endcase
end end
assign SXExp = {2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - (`NE+2)'(`BIAS); assign SXExp = {2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - (`NE+2)'(`BIAS);
assign SExp = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias}; assign SExp = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};

2
src/fpu/fdivsqrt/fdivsqrtfgen2.sv
View file

@ -29,7 +29,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module fdivsqrtfgen2 ( module fdivsqrtfgen2 (
input logic up, uz, input logic up, uz,
input logic [`DIVb+3:0] C, U, UM, input logic [`DIVb+3:0] C, U, UM,
output logic [`DIVb+3:0] F output logic [`DIVb+3:0] F
); );

2
src/fpu/fdivsqrt/fdivsqrtfgen4.sv
View file

@ -29,7 +29,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module fdivsqrtfgen4 ( module fdivsqrtfgen4 (
input logic [3:0] udigit, input logic [3:0] udigit,
input logic [`DIVb+3:0] C, U, UM, input logic [`DIVb+3:0] C, U, UM,
output logic [`DIVb+3:0] F output logic [`DIVb+3:0] F
); );

38
src/fpu/fdivsqrt/fdivsqrtfsm.sv
View file

@ -29,24 +29,24 @@
`include "wally-config.vh" `include "wally-config.vh"
module fdivsqrtfsm( module fdivsqrtfsm(
input logic clk, input logic clk,
input logic reset, input logic reset,
input logic [`FMTBITS-1:0] FmtE, input logic [`FMTBITS-1:0] FmtE,
input logic XInfE, YInfE, input logic XInfE, YInfE,
input logic XZeroE, YZeroE, input logic XZeroE, YZeroE,
input logic XNaNE, YNaNE, input logic XNaNE, YNaNE,
input logic FDivStartE, IDivStartE, input logic FDivStartE, IDivStartE,
input logic XsE, input logic XsE,
input logic SqrtE, input logic SqrtE,
input logic StallM, input logic StallM,
input logic FlushE, input logic FlushE,
input logic WZeroE, input logic WZeroE,
input logic IntDivE, input logic IntDivE,
input logic [`DIVBLEN:0] nE, input logic [`DIVBLEN:0] nE,
input logic ISpecialCaseE, input logic ISpecialCaseE,
output logic IFDivStartE, output logic IFDivStartE,
output logic FDivBusyE, FDivDoneE, output logic FDivBusyE, FDivDoneE,
output logic SpecialCaseM output logic SpecialCaseM
); );
typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype; typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;
@ -71,6 +71,7 @@ module fdivsqrtfsm(
// NS = NF + 1 // NS = NF + 1
// N = NS or NS+2 for div/sqrt. // N = NS or NS+2 for div/sqrt.
// *** CT 4/13/23 move cycles calculation back to preprocesor
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
logic [`DURLEN+1:0] Nf, fbits; // number of fractional bits logic [`DURLEN+1:0] Nf, fbits; // number of fractional bits
if (`FPSIZES == 1) if (`FPSIZES == 1)
@ -110,7 +111,8 @@ module fdivsqrtfsm(
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (reset | FlushE) begin if (reset | FlushE) begin
state <= #1 IDLE; state <= #1 IDLE;
end else if ((state == IDLE) & IFDivStartE) begin end else if (IFDivStartE) begin // IFDivStartE implies stat is IDLE
// end else if ((state == IDLE) & IFDivStartE) begin // IFDivStartE implies stat is IDLE
step <= cycles; step <= cycles;
if (SpecialCaseE) state <= #1 DONE; if (SpecialCaseE) state <= #1 DONE;
else state <= #1 BUSY; else state <= #1 BUSY;

8
src/fpu/fdivsqrt/fdivsqrtiter.sv
View file

@ -29,10 +29,10 @@
`include "wally-config.vh" `include "wally-config.vh"
module fdivsqrtiter( module fdivsqrtiter(
input logic clk, input logic clk,
input logic IFDivStartE, input logic IFDivStartE,
input logic FDivBusyE, input logic FDivBusyE,
input logic SqrtE, input logic SqrtE,
input logic [`DIVb+3:0] X, input logic [`DIVb+3:0] X,
input logic [`DIVb-1:0] DPreproc, input logic [`DIVb-1:0] DPreproc,
output logic [`DIVb-1:0] D, output logic [`DIVb-1:0] D,

2
src/fpu/fdivsqrt/fdivsqrtpostproc.sv
View file

@ -112,7 +112,7 @@ module fdivsqrtpostproc(
// Select quotient or remainder and do normalization shift // Select quotient or remainder and do normalization shift
mux2 #(`DIVBLEN+1) normshiftmux(((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR))), (mM + (`DIVBLEN+1)'(`DIVa)), RemOpM, NormShiftM); mux2 #(`DIVBLEN+1) normshiftmux(((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR))), (mM + (`DIVBLEN+1)'(`DIVa)), RemOpM, NormShiftM);
mux2 #(`DIVb+4) presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM); mux2 #(`DIVb+4) presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM);
assign PreIntResultM = $signed(PreResultM >>> NormShiftM); assign PreIntResultM = $signed(PreResultM >>> NormShiftM);
// special case logic // special case logic

12
src/fpu/fdivsqrt/fdivsqrtpreproc.sv
View file

@ -101,17 +101,19 @@ module fdivsqrtpreproc (
lzc #(`DIVb) lzcX (IFX, ell); lzc #(`DIVb) lzcX (IFX, ell);
lzc #(`DIVb) lzcY (IFD, mE); lzc #(`DIVb) lzcY (IFD, mE);
// Normalization shift // Normalization shift: shift off leading one
assign XPreproc = IFX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); // *** try to remove this +1 assign XPreproc = (IFX << ell) << 1;
assign DPreproc = IFD << (mE + {{`DIVBLEN{1'b0}}, 1'b1}); assign DPreproc = (IFD << mE) << 1;
// append leading 1 (for normal inputs) // append leading 1 (for nonzero inputs)
// shift square root to be in range [1/4, 1) // shift square root to be in range [1/4, 1)
// Normalized numbers are shifted right by 1 if the exponent is odd // Normalized numbers are shifted right by 1 if the exponent is odd
// Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd. // Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd.
mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX); mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
assign DivX = {3'b000, ~NumerZeroE, XPreproc}; assign DivX = {3'b000, ~NumerZeroE, XPreproc};
// *** CT 4/13/23 Create D output here with leading 1 appended as well, use in the other modules
// ***CT: factor out fdivsqrtcycles
if (`IDIV_ON_FPU) begin:intrightshift // Int Supported if (`IDIV_ON_FPU) begin:intrightshift // Int Supported
logic [`DIVBLEN:0] ZeroDiff, p; logic [`DIVBLEN:0] ZeroDiff, p;
logic ALTBE; logic ALTBE;
@ -119,7 +121,7 @@ module fdivsqrtpreproc (
// calculate number of fractional bits p // calculate number of fractional bits p
assign ZeroDiff = mE - ell; // Difference in number of leading zeros assign ZeroDiff = mE - ell; // Difference in number of leading zeros
assign ALTBE = ZeroDiff[`DIVBLEN]; // A less than B (A has more leading zeros) assign ALTBE = ZeroDiff[`DIVBLEN]; // A less than B (A has more leading zeros)
mux2 #(`DIVBLEN+1) pmux(ZeroDiff, {(`DIVBLEN+1){1'b0}}, ALTBE, p); // *** is there a more graceful way to write these constants mux2 #(`DIVBLEN+1) pmux(ZeroDiff, '0, ALTBE, p);
// Integer special cases (terminate immediately) // Integer special cases (terminate immediately)
assign ISpecialCaseE = BZeroE | ALTBE; assign ISpecialCaseE = BZeroE | ALTBE;

2
src/fpu/fdivsqrt/fdivsqrtqsel2.sv
View file

@ -30,7 +30,7 @@
module fdivsqrtqsel2 ( module fdivsqrtqsel2 (
input logic [3:0] ps, pc, input logic [3:0] ps, pc,
output logic up, uz, un output logic up, uz, un
); );
logic [3:0] p, g; logic [3:0] p, g;

6
src/fpu/fdivsqrt/fdivsqrtstage4.sv
View file

@ -31,7 +31,7 @@
module fdivsqrtstage4 ( module fdivsqrtstage4 (
input logic [`DIVb-1:0] D, input logic [`DIVb-1:0] D,
input logic [`DIVb+3:0] DBar, D2, DBar2, input logic [`DIVb+3:0] DBar, D2, DBar2,
input logic [`DIVb:0] U,UM, input logic [`DIVb:0] U,UM,
input logic [`DIVb+3:0] WS, WC, input logic [`DIVb+3:0] WS, WC,
input logic [`DIVb+1:0] C, input logic [`DIVb+1:0] C,
input logic SqrtE, j1, input logic SqrtE, j1,
@ -58,8 +58,8 @@ module fdivsqrtstage4 (
// 0000 = 0 // 0000 = 0
// 0010 = -1 // 0010 = -1
// 0001 = -2 // 0001 = -2
assign Smsbs = U[`DIVb:`DIVb-4]; assign Smsbs = U[`DIVb:`DIVb-4];
assign Dmsbs = D[`DIVb-1:`DIVb-3]; assign Dmsbs = D[`DIVb-1:`DIVb-3];
assign WCmsbs = WC[`DIVb+3:`DIVb-4]; assign WCmsbs = WC[`DIVb+3:`DIVb-4];
assign WSmsbs = WS[`DIVb+3:`DIVb-4]; assign WSmsbs = WS[`DIVb+3:`DIVb-4];

6
src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
View file

@ -32,10 +32,10 @@
// Unified OTFC, Radix 2 // // Unified OTFC, Radix 2 //
/////////////////////////////// ///////////////////////////////
module fdivsqrtuotfc2( module fdivsqrtuotfc2(
input logic up, un, input logic up, un,
input logic [`DIVb+1:0] C, input logic [`DIVb+1:0] C,
input logic [`DIVb:0] U, UM, input logic [`DIVb:0] U, UM,
output logic [`DIVb:0] UNext, UMNext output logic [`DIVb:0] UNext, UMNext
); );
// The on-the-fly converter transfers the divsqrt // The on-the-fly converter transfers the divsqrt
// bits to the quotient as they come. // bits to the quotient as they come.

2
src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
View file

@ -29,7 +29,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module fdivsqrtuotfc4( module fdivsqrtuotfc4(
input logic [3:0] udigit, input logic [3:0] udigit,
input logic [`DIVb:0] U, UM, input logic [`DIVb:0] U, UM,
input logic [`DIVb:0] C, input logic [`DIVb:0] C,
output logic [`DIVb:0] UNext, UMNext output logic [`DIVb:0] UNext, UMNext

2
src/fpu/fsgninj.sv
View file

@ -48,7 +48,7 @@ module fsgninj (
// format final result based on precision // format final result based on precision
// - uses NaN-blocking format // - uses NaN-blocking format
// - if there are any unsused bits the most significant bits are filled with 1s // - if there are any unused bits the most significant bits are filled with 1s
if (`FPSIZES == 1) if (`FPSIZES == 1)
assign SgnRes = {ResSgn, X[`FLEN-2:0]}; assign SgnRes = {ResSgn, X[`FLEN-2:0]};

4
src/fpu/postproc/round.sv
View file

@ -111,7 +111,7 @@ module round(
// determine what format the final result is in: int or fp // determine what format the final result is in: int or fp
assign IntRes = CvtOp & ToInt; assign IntRes = ToInt;
assign FpRes = ~IntRes; assign FpRes = ~IntRes;
// sticky bit calculation // sticky bit calculation
@ -328,4 +328,4 @@ module round(
assign Re = FullRe[`NE-1:0]; assign Re = FullRe[`NE-1:0];
endmodule endmodule

2
src/generic/lzc.sv
View file

@ -24,7 +24,7 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module lzc #(parameter WIDTH = 1) ( module lzc #(parameter WIDTH = 1) (
input logic [WIDTH-1:0] num, // number to count the leading zeroes of input logic [WIDTH-1:0] num, // number to count the leading zeroes of
output logic [$clog2(WIDTH+1)-1:0] ZeroCnt // the number of leading zeroes output logic [$clog2(WIDTH+1)-1:0] ZeroCnt // the number of leading zeroes
); );

2
src/generic/mux.sv
View file

@ -40,7 +40,7 @@ module mux3 #(parameter WIDTH = 8) (
input logic [1:0] s, input logic [1:0] s,
output logic [WIDTH-1:0] y); output logic [WIDTH-1:0] y);
assign y = s[1] ? d2 : (s[0] ? d1 : d0); assign y = s[1] ? d2 : (s[0] ? d1 : d0); // exclusion-tag: mux3
endmodule endmodule
module mux4 #(parameter WIDTH = 8) ( module mux4 #(parameter WIDTH = 8) (

2
src/generic/onehotdecoder.sv
View file

@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// oneHotDecoder.sv // onehotdecoder.sv
// //
// Written: ross1728@gmail.com July 09, 2021 // Written: ross1728@gmail.com July 09, 2021
// Modified: // Modified:

14
src/hazard/hazard.sv
View file

@ -30,13 +30,13 @@
module hazard ( module hazard (
// Detect hazards // Detect hazards
input logic BPWrongE, CSRWriteFenceM, RetM, TrapM, input logic BPWrongE, CSRWriteFenceM, RetM, TrapM,
input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD, input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
input logic LSUStallM, IFUStallF, input logic LSUStallM, IFUStallF,
input logic FCvtIntStallD, FPUStallD, input logic FCvtIntStallD, FPUStallD,
input logic DivBusyE, FDivBusyE, input logic DivBusyE, FDivBusyE,
input logic EcallFaultM, BreakpointFaultM, input logic EcallFaultM, BreakpointFaultM,
input logic wfiM, IntPendingM, input logic wfiM, IntPendingM,
// Stall & flush outputs // Stall & flush outputs
output logic StallF, StallD, StallE, StallM, StallW, output logic StallF, StallD, StallE, StallM, StallW,
output logic FlushD, FlushE, FlushM, FlushW output logic FlushD, FlushE, FlushM, FlushW

2
src/ieu/bmu/byte.sv
View file

@ -31,7 +31,7 @@
module byteUnit #(parameter WIDTH=32) ( module byteUnit #(parameter WIDTH=32) (
input logic [WIDTH-1:0] A, // Operands input logic [WIDTH-1:0] A, // Operands
input logic ByteSelect, // LSB of Immediate input logic ByteSelect, // LSB of Immediate
output logic [WIDTH-1:0] ByteResult); // rev8, orcb result output logic [WIDTH-1:0] ByteResult); // rev8, orcb result
logic [WIDTH-1:0] OrcBResult, Rev8Result; logic [WIDTH-1:0] OrcBResult, Rev8Result;

4
src/ieu/bmu/cnt.sv
View file

@ -32,8 +32,8 @@
module cnt #(parameter WIDTH = 32) ( module cnt #(parameter WIDTH = 32) (
input logic [WIDTH-1:0] A, RevA, // Operands input logic [WIDTH-1:0] A, RevA, // Operands
input logic [1:0] B, // Last 2 bits of immediate input logic [1:0] B, // Last 2 bits of immediate
input logic W64, // Indicates word operation input logic W64, // Indicates word operation
output logic [WIDTH-1:0] CntResult // count result output logic [WIDTH-1:0] CntResult // count result
); );

2
src/ieu/bmu/ext.sv
View file

@ -32,7 +32,7 @@
module ext #(parameter WIDTH = 32) ( module ext #(parameter WIDTH = 32) (
input logic [WIDTH-1:0] A, // Operands input logic [WIDTH-1:0] A, // Operands
input logic [1:0] ExtSelect, // B[2], B[0] of immediate input logic [1:0] ExtSelect, // B[2], B[0] of immediate
output logic [WIDTH-1:0] ExtResult); // Extend Result output logic [WIDTH-1:0] ExtResult); // Extend Result
logic [WIDTH-1:0] sexthResult, zexthResult, sextbResult; logic [WIDTH-1:0] sexthResult, zexthResult, sextbResult;

2
src/ieu/bmu/popcnt.sv
View file

@ -27,7 +27,7 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module popcnt #(parameter WIDTH = 32) ( module popcnt #(parameter WIDTH = 32) (
input logic [WIDTH-1:0] num, // number to count total ones input logic [WIDTH-1:0] num, // number to count total ones
output logic [$clog2(WIDTH):0] PopCnt // the total number of ones output logic [$clog2(WIDTH):0] PopCnt // the total number of ones
); );

2
src/ieu/controller.sv
View file

@ -300,7 +300,7 @@ module controller(
assign FlushDCacheD = 0; assign FlushDCacheD = 0;
end end
// Decocde stage pipeline control register // Decode stage pipeline control register
flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
// Execute stage pipeline control register and logic // Execute stage pipeline control register and logic

3
src/ieu/datapath.sv
View file

@ -138,7 +138,8 @@ module datapath (
assign MulDivResultW = MDUResultW; assign MulDivResultW = MDUResultW;
end end
end else begin:fpmux end else begin:fpmux
assign IFResultM = IEUResultM; assign IFCvtResultW = IFResultW; assign IFResultM = IEUResultM;
assign IFCvtResultW = IFResultW;
assign MulDivResultW = MDUResultW; assign MulDivResultW = MDUResultW;
end end
mux5 #(`XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); mux5 #(`XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW);

2
src/ieu/ieu.sv
View file

@ -29,7 +29,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module ieu ( module ieu (
input logic clk, reset, input logic clk, reset,
// Decode stage signals // Decode stage signals
input logic [31:0] InstrD, // Instruction input logic [31:0] InstrD, // Instruction
input logic IllegalIEUFPUInstrD, // Illegal instruction input logic IllegalIEUFPUInstrD, // Illegal instruction

2
src/ieu/regfile.sv
View file

@ -32,7 +32,7 @@
module regfile ( module regfile (
input logic clk, reset, input logic clk, reset,
input logic we3, // Write enable input logic we3, // Write enable
input logic [ 4:0] a1, a2, a3, // Source registers to read (a1, a2), destination register to write (a3) input logic [4:0] a1, a2, a3, // Source registers to read (a1, a2), destination register to write (a3)
input logic [`XLEN-1:0] wd3, // Write data for port 3 input logic [`XLEN-1:0] wd3, // Write data for port 3
output logic [`XLEN-1:0] rd1, rd2); // Read data for ports 1, 2 output logic [`XLEN-1:0] rd1, rd2); // Read data for ports 1, 2

8
src/ieu/shifter.sv
View file

@ -32,12 +32,12 @@
module shifter ( module shifter (
input logic [`XLEN-1:0] A, // shift Source input logic [`XLEN-1:0] A, // shift Source
input logic [`LOG_XLEN-1:0] Amt, // Shift amount input logic [`LOG_XLEN-1:0] Amt, // Shift amount
input logic Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift input logic Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift
output logic [`XLEN-1:0] Y); // Shifted result output logic [`XLEN-1:0] Y); // Shifted result
logic [2*`XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits logic [2*`XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
logic [`LOG_XLEN-1:0] TruncAmt, Offset; // Shift amount adjusted for RV64, right-shift amount logic [`LOG_XLEN-1:0] TruncAmt, Offset; // Shift amount adjusted for RV64, right-shift amount
logic Sign; // Sign bit for sign extension logic Sign; // Sign bit for sign extension
assign Sign = A[`XLEN-1] & SubArith; // sign bit for sign extension assign Sign = A[`XLEN-1] & SubArith; // sign bit for sign extension
if (`XLEN==32) begin // rv32 if (`XLEN==32) begin // rv32

26
src/ifu/bpred/bpred.sv
View file

@ -48,25 +48,25 @@ module bpred (
input logic [`XLEN-1:0] PCE, // Execution stage instruction address input logic [`XLEN-1:0] PCE, // Execution stage instruction address
input logic [`XLEN-1:0] PCM, // Memory stage instruction address input logic [`XLEN-1:0] PCM, // Memory stage instruction address
input logic [31:0] PostSpillInstrRawF, // Instruction input logic [31:0] PostSpillInstrRawF, // Instruction
// Branch and jump outcome // Branch and jump outcome
input logic InstrValidD, InstrValidE, input logic InstrValidD, InstrValidE,
input logic BranchD, BranchE, input logic BranchD, BranchE,
input logic JumpD, JumpE, input logic JumpD, JumpE,
input logic PCSrcE, // Executation stage branch is taken input logic PCSrcE, // Executation stage branch is taken
input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address
input logic [`XLEN-1:0] IEUAdrM, // The branch/jump target address input logic [`XLEN-1:0] IEUAdrM, // The branch/jump target address
input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as call, return, jr (not return), j, br output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as call, return, jr (not return), j, br
// Report branch prediction status // Report branch prediction status
output logic BPWrongE, // Prediction is wrong output logic BPWrongE, // Prediction is wrong
output logic BPWrongM, // Prediction is wrong output logic BPWrongM, // Prediction is wrong
output logic BPDirPredWrongM, // Prediction direction is wrong output logic BPDirPredWrongM, // Prediction direction is wrong
output logic BTAWrongM, // Prediction target wrong output logic BTAWrongM, // Prediction target wrong
output logic RASPredPCWrongM, // RAS prediction is wrong output logic RASPredPCWrongM, // RAS prediction is wrong
output logic IClassWrongM // Class prediction is wrong output logic IClassWrongM // Class prediction is wrong
); );
logic [1:0] BPDirPredF; logic [1:0] BPDirPredF;
@ -187,7 +187,7 @@ module bpred (
// Correct branch/jump target. // Correct branch/jump target.
mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE); mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE);
// If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE. // If the fence/csrw was predicted as a taken branch then we select PCF, rather than PCE.
// Effectively this is PCM+4 or the non-existant PCLinkM // Effectively this is PCM+4 or the non-existant PCLinkM
if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE); if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE);
else assign NextValidPCE = PCE; else assign NextValidPCE = PCE;
@ -201,11 +201,11 @@ module bpred (
// 3. target ras (ras target wrong / class[2]) // 3. target ras (ras target wrong / class[2])
// 4. direction (br dir wrong / class[0]) // 4. direction (br dir wrong / class[0])
// Unforuantely we can't use PCD to infer the correctness of the BTB or RAS because the class prediction // Unfortunately we can't use PCD to infer the correctness of the BTB or RAS because the class prediction
// could be wrong or the fall through address selected for branch predict not taken. // could be wrong or the fall through address selected for branch predict not taken.
// By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
// both without the above inaccuracies. // both without the above inaccuracies.
// **** use BPBTAWrongM from BTB. // **** use BPBTAWrongM from BTB.
assign BTAWrongE = (BPBTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE; assign BTAWrongE = (BPBTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE;
assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE; assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE;

22
src/ifu/bpred/btb.sv
View file

@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// btb.sv // btb.sv
// //
// Written: Ross Thomposn ross1728@gmail.com // Written: Ross Thompson ross1728@gmail.com
// Created: February 15, 2021 // Created: February 15, 2021
// Modified: 24 January 2023 // Modified: 24 January 2023
// //
@ -34,19 +34,19 @@ module btb #(parameter Depth = 10 ) (
input logic clk, input logic clk,
input logic reset, input logic reset,
input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW, input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW,
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,// PC at various stages input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages
output logic [`XLEN-1:0] BPBTAF, // BTB's guess at PC output logic [`XLEN-1:0] BPBTAF, // BTB's guess at PC
output logic [`XLEN-1:0] BPBTAD, output logic [`XLEN-1:0] BPBTAD,
output logic [`XLEN-1:0] BPBTAE, output logic [`XLEN-1:0] BPBTAE,
output logic [3:0] BTBIClassF, // BTB's guess at instruction class output logic [3:0] BTBIClassF, // BTB's guess at instruction class
// update // update
input logic IClassWrongM, // BTB's instruction class guess was wrong input logic IClassWrongM, // BTB's instruction class guess was wrong
input logic IClassWrongE, input logic IClassWrongE,
input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb
input logic [`XLEN-1:0] IEUAdrM, // Branch/jump target address to insert into btb input logic [`XLEN-1:0] IEUAdrM, // Branch/jump target address to insert into btb
input logic [3:0] InstrClassD, // Instruction class to insert into btb input logic [3:0] InstrClassD, // Instruction class to insert into btb
input logic [3:0] InstrClassE, // Instruction class to insert into btb input logic [3:0] InstrClassE, // Instruction class to insert into btb
input logic [3:0] InstrClassM, // Instruction class to insert into btb input logic [3:0] InstrClassM, // Instruction class to insert into btb
input logic [3:0] InstrClassW input logic [3:0] InstrClassW
); );
@ -73,7 +73,7 @@ module btb #(parameter Depth = 10 ) (
// must output a valid PC and valid bit during reset. Because only PCF, not PCNextF is reset, PCNextF is invalid // must output a valid PC and valid bit during reset. Because only PCF, not PCNextF is reset, PCNextF is invalid
// during reset. The BTB must produce a non X PC1NextF to allow the simulation to run. // during reset. The BTB must produce a non X PC1NextF to allow the simulation to run.
// While thie mux could be included in IFU it is not necessary for the IROM/I$/bus. // While the mux could be included in IFU it is not necessary for the IROM/I$/bus.
// For now it is optimal to leave it here. // For now it is optimal to leave it here.
assign ResetPC = `RESET_VECTOR; assign ResetPC = `RESET_VECTOR;
assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};

2
src/ifu/decompress.sv
View file

@ -44,7 +44,7 @@ module decompress (
logic [5:0] immSH; logic [5:0] immSH;
logic [1:0] op; logic [1:0] op;
// Extrac op and register source/destination fields // Extract op and register source/destination fields
assign instr16 = InstrRawD[15:0]; // instruction is already aligned assign instr16 = InstrRawD[15:0]; // instruction is already aligned
assign op = instr16[1:0]; assign op = instr16[1:0];
assign rds1 = instr16[11:7]; assign rds1 = instr16[11:7];

6
src/ifu/ifu.sv
View file

@ -4,7 +4,7 @@
// Written: David_Harris@hmc.edu 9 January 2021 // Written: David_Harris@hmc.edu 9 January 2021
// Modified: // Modified:
// //
// Purpose: Instrunction Fetch Unit // Purpose: Instruction Fetch Unit
// PC, branch prediction, instruction cache // PC, branch prediction, instruction cache
// //
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
@ -362,7 +362,7 @@ module ifu (
assign IllegalIEUFPUInstrD = IllegalIEUInstrD & IllegalFPUInstrD; assign IllegalIEUFPUInstrD = IllegalIEUInstrD & IllegalFPUInstrD;
// Misaligned PC logic // Misaligned PC logic
// Instruction address misalignement only from br/jal(r) instructions. // Instruction address misalignment only from br/jal(r) instructions.
// instruction address misalignment is generated by the target of control flow instructions, not // instruction address misalignment is generated by the target of control flow instructions, not
// the fetch itself. // the fetch itself.
// xret and Traps both cannot produce instruction misaligned. // xret and Traps both cannot produce instruction misaligned.
@ -372,7 +372,7 @@ module ifu (
// Spec 3.1.14 // Spec 3.1.14
// Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec. // Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec.
assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE; assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM); flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
// Instruction and PC/PCLink pipeline registers // Instruction and PC/PCLink pipeline registers
// Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0. // Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0.

4
src/mdu/mdu.sv
View file

@ -69,8 +69,8 @@ module mdu(
3'b001: PrelimResultM = ProdM[`XLEN*2-1:`XLEN]; // mulh 3'b001: PrelimResultM = ProdM[`XLEN*2-1:`XLEN]; // mulh
3'b010: PrelimResultM = ProdM[`XLEN*2-1:`XLEN]; // mulhsu 3'b010: PrelimResultM = ProdM[`XLEN*2-1:`XLEN]; // mulhsu
3'b011: PrelimResultM = ProdM[`XLEN*2-1:`XLEN]; // mulhu 3'b011: PrelimResultM = ProdM[`XLEN*2-1:`XLEN]; // mulhu
3'b100: PrelimResultM = QuotM; // div 3'b100: PrelimResultM = QuotM; // div
3'b101: PrelimResultM = QuotM; // divu 3'b101: PrelimResultM = QuotM; // divu
3'b110: PrelimResultM = RemM; // rem 3'b110: PrelimResultM = RemM; // rem
3'b111: PrelimResultM = RemM; // remu 3'b111: PrelimResultM = RemM; // remu
endcase endcase

16
src/mmu/mmu.sv
View file

@ -49,14 +49,14 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
output logic Idempotent, // PMA indicates memory address is idempotent output logic Idempotent, // PMA indicates memory address is idempotent
output logic SelTIM, // Select a tightly integrated memory output logic SelTIM, // Select a tightly integrated memory
// Faults // Faults
output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources
output logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM, // page fault sources output logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM, // page fault sources
output logic UpdateDA, // page fault due to setting dirty or access bit output logic UpdateDA, // page fault due to setting dirty or access bit
output logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned fault sources output logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned fault sources
// PMA checker signals // PMA checker signals
input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // access type input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // access type
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration
input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP addresses input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP addresses
); );
logic [`PA_BITS-1:0] TLBPAdr; // physical address for TLB logic [`PA_BITS-1:0] TLBPAdr; // physical address for TLB
@ -86,7 +86,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
.DisableTranslation, .PTE, .PageTypeWriteVal, .DisableTranslation, .PTE, .PageTypeWriteVal,
.TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit, .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit,
.Translate, .TLBPageFault, .UpdateDA); .Translate, .TLBPageFault, .UpdateDA);
end else begin:tlb// just pass address through as physical end else begin:tlb // just pass address through as physical
assign Translate = 0; assign Translate = 0;
assign TLBMiss = 0; assign TLBMiss = 0;
assign TLBHit = 1; // *** is this necessary assign TLBHit = 1; // *** is this necessary

5
src/privileged/csrsr.sv
View file

@ -93,7 +93,7 @@ module csrsr (
// harwired STATUS bits // harwired STATUS bits
assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported
assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override reigster with 0 if only machine mode supported assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override register with 0 if only machine mode supported
assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported
assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported
/* assign STATUS_UBE = 0; // little-endian /* assign STATUS_UBE = 0; // little-endian
@ -198,9 +198,12 @@ module csrsr (
STATUS_UBE <= #1 CSRWriteValM[6] & `U_SUPPORTED & `BIGENDIAN_SUPPORTED; STATUS_UBE <= #1 CSRWriteValM[6] & `U_SUPPORTED & `BIGENDIAN_SUPPORTED;
STATUS_MBE <= #1 nextMBE; STATUS_MBE <= #1 nextMBE;
STATUS_SBE <= #1 nextSBE; STATUS_SBE <= #1 nextSBE;
// coverage off
// MSTATUSH only exists in 32-bit configurations, will not be hit on rv64gc
end else if (WriteMSTATUSHM) begin end else if (WriteMSTATUSHM) begin
STATUS_MBE <= #1 CSRWriteValM[5] & `BIGENDIAN_SUPPORTED; STATUS_MBE <= #1 CSRWriteValM[5] & `BIGENDIAN_SUPPORTED;
STATUS_SBE <= #1 CSRWriteValM[4] & `S_SUPPORTED & `BIGENDIAN_SUPPORTED; STATUS_SBE <= #1 CSRWriteValM[4] & `S_SUPPORTED & `BIGENDIAN_SUPPORTED;
// coverage on
end else if (WriteSSTATUSM) begin // write a subset of the STATUS bits end else if (WriteSSTATUSM) begin // write a subset of the STATUS bits
STATUS_MXR_INT <= #1 CSRWriteValM[19]; STATUS_MXR_INT <= #1 CSRWriteValM[19];
STATUS_SUM_INT <= #1 CSRWriteValM[18]; STATUS_SUM_INT <= #1 CSRWriteValM[18];

3
src/privileged/trap.sv
View file

@ -81,11 +81,14 @@ module trap (
/////////////////////////////////////////// ///////////////////////////////////////////
assign BothInstrAccessFaultM = InstrAccessFaultM | HPTWInstrAccessFaultM; assign BothInstrAccessFaultM = InstrAccessFaultM | HPTWInstrAccessFaultM;
// coverage off -item e 1 -fecexprrow 2
// excludes InstrMisalignedFaultM from coverage of this line, since misaligned instructions cannot occur in rv64gc.
assign ExceptionM = InstrMisalignedFaultM | BothInstrAccessFaultM | IllegalInstrFaultM | assign ExceptionM = InstrMisalignedFaultM | BothInstrAccessFaultM | IllegalInstrFaultM |
LoadMisalignedFaultM | StoreAmoMisalignedFaultM | LoadMisalignedFaultM | StoreAmoMisalignedFaultM |
InstrPageFaultM | LoadPageFaultM | StoreAmoPageFaultM | InstrPageFaultM | LoadPageFaultM | StoreAmoPageFaultM |
BreakpointFaultM | EcallFaultM | BreakpointFaultM | EcallFaultM |
LoadAccessFaultM | StoreAmoAccessFaultM; LoadAccessFaultM | StoreAmoAccessFaultM;
// coverage on
assign TrapM = ExceptionM | InterruptM; assign TrapM = ExceptionM | InterruptM;
assign RetM = mretM | sretM; assign RetM = mretM | sretM;

587
testbench/testbench.sv
View file

@ -49,32 +49,32 @@ module testbench;
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
logic [31:0] InstrW; logic [31:0] InstrW;
string tests[]; string tests[];
logic [3:0] dummy; logic [3:0] dummy;
logic [`AHBW-1:0] HRDATAEXT; logic [`AHBW-1:0] HRDATAEXT;
logic HREADYEXT, HRESPEXT; logic HREADYEXT, HRESPEXT;
logic [`PA_BITS-1:0] HADDR; logic [`PA_BITS-1:0] HADDR;
logic [`AHBW-1:0] HWDATA; logic [`AHBW-1:0] HWDATA;
logic [`XLEN/8-1:0] HWSTRB; logic [`XLEN/8-1:0] HWSTRB;
logic HWRITE; logic HWRITE;
logic [2:0] HSIZE; logic [2:0] HSIZE;
logic [2:0] HBURST; logic [2:0] HBURST;
logic [3:0] HPROT; logic [3:0] HPROT;
logic [1:0] HTRANS; logic [1:0] HTRANS;
logic HMASTLOCK; logic HMASTLOCK;
logic HCLK, HRESETn; logic HCLK, HRESETn;
logic [`XLEN-1:0] PCW; logic [`XLEN-1:0] PCW;
string ProgramAddrMapFile, ProgramLabelMapFile; string ProgramAddrMapFile, ProgramLabelMapFile;
integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 }; integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
logic DCacheFlushDone, DCacheFlushStart; logic DCacheFlushDone, DCacheFlushStart;
logic riscofTest; logic riscofTest;
logic StartSample, EndSample; logic StartSample, EndSample;
flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW);
// check assertions for a legal configuration // check assertions for a legal configuration
riscvassertions riscvassertions(); riscvassertions riscvassertions();
@ -85,62 +85,62 @@ logic [3:0] dummy;
//tests = '{}; //tests = '{};
if (`XLEN == 64) begin // RV64 if (`XLEN == 64) begin // RV64
case (TEST) case (TEST)
"arch64i": tests = arch64i; "arch64i": tests = arch64i;
"arch64priv": tests = arch64priv; "arch64priv": tests = arch64priv;
"arch64c": if (`C_SUPPORTED) "arch64c": if (`C_SUPPORTED)
if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv}; if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
else tests = {arch64c}; else tests = {arch64c};
"arch64m": if (`M_SUPPORTED) tests = arch64m; "arch64m": if (`M_SUPPORTED) tests = arch64m;
"arch64f": if (`F_SUPPORTED) tests = arch64f; "arch64f": if (`F_SUPPORTED) tests = arch64f;
"arch64d": if (`D_SUPPORTED) tests = arch64d; "arch64d": if (`D_SUPPORTED) tests = arch64d;
"arch64zi": if (`ZIFENCEI_SUPPORTED) tests = arch64zi; "arch64zi": if (`ZIFENCEI_SUPPORTED) tests = arch64zi;
"imperas64i": tests = imperas64i; "imperas64i": tests = imperas64i;
"imperas64f": if (`F_SUPPORTED) tests = imperas64f; "imperas64f": if (`F_SUPPORTED) tests = imperas64f;
"imperas64d": if (`D_SUPPORTED) tests = imperas64d; "imperas64d": if (`D_SUPPORTED) tests = imperas64d;
"imperas64m": if (`M_SUPPORTED) tests = imperas64m; "imperas64m": if (`M_SUPPORTED) tests = imperas64m;
"wally64a": if (`A_SUPPORTED) tests = wally64a; "wally64a": if (`A_SUPPORTED) tests = wally64a;
"imperas64c": if (`C_SUPPORTED) tests = imperas64c; "imperas64c": if (`C_SUPPORTED) tests = imperas64c;
else tests = imperas64iNOc; else tests = imperas64iNOc;
"custom": tests = custom; "custom": tests = custom;
"wally64i": tests = wally64i; "wally64i": tests = wally64i;
"wally64priv": tests = wally64priv; "wally64priv": tests = wally64priv;
"wally64periph": tests = wally64periph; "wally64periph": tests = wally64periph;
"coremark": tests = coremark; "coremark": tests = coremark;
"fpga": tests = fpga; "fpga": tests = fpga;
"ahb" : tests = ahb; "ahb" : tests = ahb;
"coverage64gc" : tests = coverage64gc; "coverage64gc" : tests = coverage64gc;
"arch64zba": if (`ZBA_SUPPORTED) tests = arch64zba; "arch64zba": if (`ZBA_SUPPORTED) tests = arch64zba;
"arch64zbb": if (`ZBB_SUPPORTED) tests = arch64zbb; "arch64zbb": if (`ZBB_SUPPORTED) tests = arch64zbb;
"arch64zbc": if (`ZBC_SUPPORTED) tests = arch64zbc; "arch64zbc": if (`ZBC_SUPPORTED) tests = arch64zbc;
"arch64zbs": if (`ZBS_SUPPORTED) tests = arch64zbs; "arch64zbs": if (`ZBS_SUPPORTED) tests = arch64zbs;
endcase endcase
end else begin // RV32 end else begin // RV32
case (TEST) case (TEST)
"arch32i": tests = arch32i; "arch32i": tests = arch32i;
"arch32priv": tests = arch32priv; "arch32priv": tests = arch32priv;
"arch32c": if (`C_SUPPORTED) "arch32c": if (`C_SUPPORTED)
if (`ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv}; if (`ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
else tests = {arch32c}; else tests = {arch32c};
"arch32m": if (`M_SUPPORTED) tests = arch32m; "arch32m": if (`M_SUPPORTED) tests = arch32m;
"arch32f": if (`F_SUPPORTED) tests = arch32f; "arch32f": if (`F_SUPPORTED) tests = arch32f;
"arch32d": if (`D_SUPPORTED) tests = arch32d; "arch32d": if (`D_SUPPORTED) tests = arch32d;
"arch32zi": if (`ZIFENCEI_SUPPORTED) tests = arch32zi; "arch32zi": if (`ZIFENCEI_SUPPORTED) tests = arch32zi;
"imperas32i": tests = imperas32i; "imperas32i": tests = imperas32i;
"imperas32f": if (`F_SUPPORTED) tests = imperas32f; "imperas32f": if (`F_SUPPORTED) tests = imperas32f;
"imperas32m": if (`M_SUPPORTED) tests = imperas32m; "imperas32m": if (`M_SUPPORTED) tests = imperas32m;
"wally32a": if (`A_SUPPORTED) tests = wally32a; "wally32a": if (`A_SUPPORTED) tests = wally32a;
"imperas32c": if (`C_SUPPORTED) tests = imperas32c; "imperas32c": if (`C_SUPPORTED) tests = imperas32c;
else tests = imperas32iNOc; else tests = imperas32iNOc;
"wally32i": tests = wally32i; "wally32i": tests = wally32i;
"wally32e": tests = wally32e; "wally32e": tests = wally32e;
"wally32priv": tests = wally32priv; "wally32priv": tests = wally32priv;
"wally32periph": tests = wally32periph; "wally32periph": tests = wally32periph;
"embench": tests = embench; "embench": tests = embench;
"coremark": tests = coremark; "coremark": tests = coremark;
"arch32zba": if (`ZBA_SUPPORTED) tests = arch32zba; "arch32zba": if (`ZBA_SUPPORTED) tests = arch32zba;
"arch32zbb": if (`ZBB_SUPPORTED) tests = arch32zbb; "arch32zbb": if (`ZBB_SUPPORTED) tests = arch32zbb;
"arch32zbc": if (`ZBC_SUPPORTED) tests = arch32zbc; "arch32zbc": if (`ZBC_SUPPORTED) tests = arch32zbc;
"arch32zbs": if (`ZBS_SUPPORTED) tests = arch32zbs; "arch32zbs": if (`ZBS_SUPPORTED) tests = arch32zbs;
endcase endcase
end end
if (tests.size() == 0) begin if (tests.size() == 0) begin
@ -149,7 +149,7 @@ logic [3:0] dummy;
end end
end end
string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile; string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile;
integer outputFilePointer; integer outputFilePointer;
logic [31:0] GPIOIN, GPIOOUT, GPIOEN; logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
@ -160,16 +160,16 @@ logic [3:0] dummy;
logic SDCCmdOut; logic SDCCmdOut;
logic SDCCmdOE; logic SDCCmdOE;
logic [3:0] SDCDatIn; logic [3:0] SDCDatIn;
tri1 [3:0] SDCDat; tri1 [3:0] SDCDat;
tri1 SDCCmd; tri1 SDCCmd;
logic HREADY; logic HREADY;
logic HSELEXT; logic HSELEXT;
logic InitializingMemories; logic InitializingMemories;
integer ResetCount, ResetThreshold; integer ResetCount, ResetThreshold;
logic InReset; logic InReset;
logic Begin; logic BeginSample;
// instantiate device to be tested // instantiate device to be tested
assign GPIOIN = 0; assign GPIOIN = 0;
@ -225,13 +225,14 @@ logic [3:0] dummy;
totalerrors = 0; totalerrors = 0;
testadr = 0; testadr = 0;
testadrNoBase = 0; testadrNoBase = 0;
// riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests and tests[0] == "2" refers to WallyRiscvArchTests // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests
// and tests[0] == "2" refers to WallyRiscvArchTests
riscofTest = tests[0] == "1" | tests[0] == "2"; riscofTest = tests[0] == "1" | tests[0] == "2";
// fill memory with defined values to reduce Xs in simulation // fill memory with defined values to reduce Xs in simulation
// Quick note the memory will need to be initialized. The C library does not // Quick note the memory will need to be initialized. The C library does not
// guarantee the initialized reads. For example a strcmp can read 6 byte // guarantee the initialized reads. For example a strcmp can read 6 byte
// strings, but uses a load double to read them in. If the last 2 bytes are // strings, but uses a load double to read them in. If the last 2 bytes are
// not initialized the compare results in an 'x' which propagates through // not initialized the compare results in an 'x' which propagates through
// the design. // the design.
if (TEST == "coremark") if (TEST == "coremark")
for (i=MemStartAddr; i<MemEndAddr; i = i+1) for (i=MemStartAddr; i<MemEndAddr; i = i+1)
@ -243,7 +244,7 @@ logic [3:0] dummy;
pathname = tvpaths[0]; pathname = tvpaths[0];
else pathname = tvpaths[1]; */ else pathname = tvpaths[1]; */
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
else memfilename = {pathname, tests[test], ".elf.memfile"}; else memfilename = {pathname, tests[test], ".elf.memfile"};
if (`FPGA) begin if (`FPGA) begin
string romfilename, sdcfilename; string romfilename, sdcfilename;
romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
@ -253,9 +254,9 @@ logic [3:0] dummy;
// force sdc timers // force sdc timers
force dut.uncore.uncore.sdc.SDC.LimitTimers = 1; force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
end else begin end else begin
if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
end end
if (riscofTest) begin if (riscofTest) begin
@ -265,8 +266,9 @@ logic [3:0] dummy;
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
end end
// declare memory labels that interest us, the updateProgramAddrLabelArray task will find the addr of each label and fill the array // declare memory labels that interest us, the updateProgramAddrLabelArray task will find
// to expand, add more elements to this array and initialize them to zero (also initilaize them to zero at the start of the next test) // the addr of each label and fill the array. To expand, add more elements to this array
// and initialize them to zero (also initilaize them to zero at the start of the next test)
if(!`FPGA) begin if(!`FPGA) begin
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
$display("Read memfile %s", memfilename); $display("Read memfile %s", memfilename);
@ -294,99 +296,99 @@ logic [3:0] dummy;
ResetCount = 0; ResetCount = 0;
end end
end else begin end else begin
if (TEST == "coremark") if (TEST == "coremark")
if (dut.core.priv.priv.EcallFaultM) begin if (dut.core.priv.priv.EcallFaultM) begin
$display("Benchmark: coremark is done."); $display("Benchmark: coremark is done.");
$stop; $stop;
end end
// Termination condition (i.e. we finished running current test) // Termination condition (i.e. we finished running current test)
if (DCacheFlushDone) begin if (DCacheFlushDone) begin
integer begin_signature_addr; integer begin_signature_addr;
InReset = 1; InReset = 1;
begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
if (!begin_signature_addr) if (!begin_signature_addr)
$display("begin_signature addr not found in %s", ProgramLabelMapFile); $display("begin_signature addr not found in %s", ProgramLabelMapFile);
testadr = ($unsigned(begin_signature_addr))/(`XLEN/8); testadr = ($unsigned(begin_signature_addr))/(`XLEN/8);
testadrNoBase = (begin_signature_addr - `UNCORE_RAM_BASE)/(`XLEN/8); testadrNoBase = (begin_signature_addr - `UNCORE_RAM_BASE)/(`XLEN/8);
#600; // give time for instructions in pipeline to finish #600; // give time for instructions in pipeline to finish
if (TEST == "embench") begin if (TEST == "embench") begin
// Writes contents of begin_signature to .sim.output file // Writes contents of begin_signature to .sim.output file
// this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score // this contains instret and cycles for start and end of test run, used by embench
// also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking // python speed script to calculate embench speed score.
// also, begin_signature contains the results of the self checking mechanism,
// which will be read by the python script for error checking
$display("Embench Benchmark: %s is done.", tests[test]); $display("Embench Benchmark: %s is done.", tests[test]);
if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"}; if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
else outputfile = {pathname, tests[test], ".sim.output"}; else outputfile = {pathname, tests[test], ".sim.output"};
outputFilePointer = $fopen(outputfile); outputFilePointer = $fopen(outputfile);
i = 0; i = 0;
while ($unsigned(i) < $unsigned(5'd5)) begin while ($unsigned(i) < $unsigned(5'd5)) begin
$fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]); $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
i = i + 1; i = i + 1;
end end
$fclose(outputFilePointer); $fclose(outputFilePointer);
$display("Embench Benchmark: created output file: %s", outputfile); $display("Embench Benchmark: created output file: %s", outputfile);
end else if (TEST == "coverage64gc") begin end else if (TEST == "coverage64gc") begin
$display("Coverage tests don't get checked"); $display("Coverage tests don't get checked");
end else begin end else begin
// for tests with no self checking mechanism, read .signature.output file and compare to check for errors // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
// clear signature to prevent contamination from previous tests // clear signature to prevent contamination from previous tests
for(i=0; i<SIGNATURESIZE; i=i+1) begin for(i=0; i<SIGNATURESIZE; i=i+1) begin
sig32[i] = 'bx; sig32[i] = 'bx;
end end
if (riscofTest) signame = {pathname, tests[test], "/ref/Reference-sail_c_simulator.signature"}; if (riscofTest) signame = {pathname, tests[test], "/ref/Reference-sail_c_simulator.signature"};
else signame = {pathname, tests[test], ".signature.output"}; else signame = {pathname, tests[test], ".signature.output"};
// read signature, reformat in 64 bits if necessary // read signature, reformat in 64 bits if necessary
$readmemh(signame, sig32); $readmemh(signame, sig32);
i = 0; i = 0;
while (i < SIGNATURESIZE) begin while (i < SIGNATURESIZE) begin
if (`XLEN == 32) begin if (`XLEN == 32) begin
signature[i] = sig32[i]; signature[i] = sig32[i];
i = i+1; i = i+1;
end else begin end else begin
signature[i/2] = {sig32[i+1], sig32[i]}; signature[i/2] = {sig32[i+1], sig32[i]};
i = i + 2; i = i + 2;
end end
if (i >= 4 & sig32[i-4] === 'bx) begin if (i >= 4 & sig32[i-4] === 'bx) begin
if (i == 4) begin if (i == 4) begin
i = SIGNATURESIZE+1; // flag empty file i = SIGNATURESIZE+1; // flag empty file
$display(" Error: empty test file"); $display(" Error: empty test file");
end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
end end
end end
// Check errors // Check errors
errors = (i == SIGNATURESIZE+1); // error if file is empty errors = (i == SIGNATURESIZE+1); // error if file is empty
i = 0; i = 0;
/* verilator lint_off INFINITELOOP */ /* verilator lint_off INFINITELOOP */
while (signature[i] !== 'bx) begin while (signature[i] !== 'bx) begin
logic [`XLEN-1:0] sig; logic [`XLEN-1:0] sig;
if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
//$display("signature[%h] = %h sig = %h", i, signature[i], sig); //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
errors = errors+1; errors = errors+1;
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
$stop;//***debug $stop; //***debug
end end
i = i + 1; i = i + 1;
end end
/* verilator lint_on INFINITELOOP */ /* verilator lint_on INFINITELOOP */
if (errors == 0) begin if (errors == 0) begin
$display("%s succeeded. Brilliant!!!", tests[test]); $display("%s succeeded. Brilliant!!!", tests[test]);
end end else begin
else begin
$display("%s failed with %d errors. :(", tests[test], errors); $display("%s failed with %d errors. :(", tests[test], errors);
totalerrors = totalerrors+1; totalerrors = totalerrors+1;
end end
end end
// move onto the next test, check to see if we're done // move onto the next test, check to see if we're done
test = test + 1; test = test + 1;
if (test == tests.size()) begin if (test == tests.size()) begin
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
else $display("FAIL: %d test programs had errors", totalerrors); else $display("FAIL: %d test programs had errors", totalerrors);
$stop; $stop;
end end else begin
else begin
InitializingMemories = 1; InitializingMemories = 1;
// If there are still additional tests to run, read in information for the next test // If there are still additional tests to run, read in information for the next test
//pathname = tvpaths[tests[0]]; //pathname = tvpaths[tests[0]];
@ -394,7 +396,7 @@ logic [3:0] dummy;
else memfilename = {pathname, tests[test], ".elf.memfile"}; else memfilename = {pathname, tests[test], ".elf.memfile"};
//$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); //$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
if (riscofTest) begin if (riscofTest) begin
@ -405,22 +407,22 @@ logic [3:0] dummy;
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
end end
ProgramAddrLabelArray = '{ "begin_signature" : 0, "tohost" : 0 }; ProgramAddrLabelArray = '{ "begin_signature" : 0, "tohost" : 0 };
if(!`FPGA) begin if(!`FPGA) begin
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
$display("Read memfile %s", memfilename); $display("Read memfile %s", memfilename);
end end
end end
end // if (DCacheFlushDone) end // if (DCacheFlushDone)
end end
end // always @ (negedge clk) end // always @ (negedge clk)
if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin : HPMCSample if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin : HPMCSample
integer HPMCindex; integer HPMCindex;
logic StartSampleFirst; logic StartSampleFirst;
logic StartSampleDelayed, BeginDelayed; logic StartSampleDelayed, BeginDelayed;
logic EndSampleFirst, EndSampleDelayed; logic EndSampleFirst, EndSampleDelayed;
logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0]; logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0];
string HPMCnames[] = '{"Mcycle", string HPMCnames[] = '{"Mcycle",
"------", "------",
@ -433,8 +435,8 @@ logic [3:0] dummy;
"BP Target Wrong", "BP Target Wrong",
"RAS Wrong", "RAS Wrong",
"Instr Class Wrong", "Instr Class Wrong",
"Load Stall", "Load Stall",
"Store Stall", "Store Stall",
"D Cache Access", "D Cache Access",
"D Cache Miss", "D Cache Miss",
"D Cache Cycles", "D Cache Cycles",
@ -447,56 +449,55 @@ logic [3:0] dummy;
"Interrupt", "Interrupt",
"Exception", "Exception",
"Divide Cycles" "Divide Cycles"
}; };
if(TEST == "embench") begin if(TEST == "embench") begin
// embench runs warmup then runs start_trigger // embench runs warmup then runs start_trigger
// embench end with stop_trigger. // embench end with stop_trigger.
assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger"; assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
assign StartSample = StartSampleFirst & ~ StartSampleDelayed; assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger"; assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
assign EndSample = EndSampleFirst & ~ EndSampleDelayed; assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
end else if(TEST == "coremark") begin end else if(TEST == "coremark") begin
// embench runs warmup then runs start_trigger // embench runs warmup then runs start_trigger
// embench end with stop_trigger. // embench end with stop_trigger.
assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time"; assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
assign StartSample = StartSampleFirst & ~ StartSampleDelayed; assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time"; assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
assign EndSample = EndSampleFirst & ~ EndSampleDelayed; assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
end else begin end else begin
// default start condiction is reset // default start condiction is reset
// default end condiction is end of test (DCacheFlushDone) // default end condiction is end of test (DCacheFlushDone)
assign StartSampleFirst = InReset; assign StartSampleFirst = InReset;
flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
assign StartSample = StartSampleFirst & ~ StartSampleDelayed; assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
assign EndSample = DCacheFlushStart & ~DCacheFlushDone; assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
assign Begin = StartSampleFirst & ~BeginDelayed; assign BeginSample = StartSampleFirst & ~BeginDelayed;
end end
always @(negedge clk) begin always @(negedge clk) begin
if(StartSample) begin if(StartSample) begin
for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex]; InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
end end
end end
if(EndSample) begin if(EndSample) begin
for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
// unlikely to have more than 10M in any counter. // unlikely to have more than 10M in any counter.
$display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex] - InitialHPMCOUNTERH[HPMCindex], HPMCnames[HPMCindex]); $display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex] - InitialHPMCOUNTERH[HPMCindex], HPMCnames[HPMCindex]);
end end
end end
end end
end end
@ -535,24 +536,24 @@ logic [3:0] dummy;
if (`BPRED_SUPPORTED) begin if (`BPRED_SUPPORTED) begin
integer adrindex; integer adrindex;
always @(*) begin always @(*) begin
if(reset) begin if(reset) begin
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
end end
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
end end
#1; #1;
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex]; release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
end end
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex]; release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
end end
end end
end end
end end
if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
@ -560,49 +561,47 @@ end
string LogFile; string LogFile;
logic resetD, resetEdge; logic resetD, resetEdge;
logic Enable; logic Enable;
// assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset; logic InvalDelayed, InvalEdge;
// this version of Enable allows for accurate eviction logging.
// Likely needs further improvement.
assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn &
dut.core.ifu.immu.immu.pmachecker.Cacheable & dut.core.ifu.immu.immu.pmachecker.Cacheable &
~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage & ~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage &
~reset; ~reset;
flop #(1) ResetDReg(clk, reset, resetD); flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD; assign resetEdge = ~reset & resetD;
flop #(1) InvalReg(clk, dut.core.ifu.InvalidateICacheM, InvalDelayed); flop #(1) InvalReg(clk, dut.core.ifu.InvalidateICacheM, InvalDelayed);
assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed; assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
initial begin initial begin
LogFile = $psprintf("ICache.log"); LogFile = $psprintf("ICache.log");
file = $fopen(LogFile, "w"); file = $fopen(LogFile, "w");
$fwrite(file, "BEGIN %s\n", memfilename); $fwrite(file, "BEGIN %s\n", memfilename);
end end
string AccessTypeString, HitMissString; string AccessTypeString, HitMissString;
assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" : assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" :
dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M"; dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
always @(posedge clk) begin always @(posedge clk) begin
if(resetEdge) $fwrite(file, "TRAIN\n"); if(resetEdge) $fwrite(file, "TRAIN\n");
if(Begin) $fwrite(file, "BEGIN %s\n", memfilename); if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
if(Enable) begin // only log i cache reads if(Enable) begin // only log i cache reads
$fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString); $fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
end end
if(InvalEdge) $fwrite(file, "0 I X\n"); if(InvalEdge) $fwrite(file, "0 I X\n");
if(EndSample) $fwrite(file, "END %s\n", memfilename); if(EndSample) $fwrite(file, "END %s\n", memfilename);
end end
end end
if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin : DCacheLogger if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin : DCacheLogger
int file; int file;
string LogFile; string LogFile;
logic resetD, resetEdge; logic resetD, resetEdge;
logic Enabled; logic Enabled;
string AccessTypeString, HitMissString; string AccessTypeString, HitMissString;
flop #(1) ResetDReg(clk, reset, resetD); flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD; assign resetEdge = ~reset & resetD;
assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" : assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" :
(!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" : (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E"; dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
@ -611,30 +610,25 @@ end
dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" :
dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
"NULL"; "NULL";
// assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.CurrState == 0) &
// ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
// (AccessTypeString != "NULL");
// This version of enable allows for accurate eviction logging.
// Likely needs further improvement.
assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn & assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn &
~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable & dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable &
(AccessTypeString != "NULL"); (AccessTypeString != "NULL");
initial begin initial begin
LogFile = $psprintf("DCache.log"); LogFile = $psprintf("DCache.log");
file = $fopen(LogFile, "w"); file = $fopen(LogFile, "w");
$fwrite(file, "BEGIN %s\n", memfilename); $fwrite(file, "BEGIN %s\n", memfilename);
end end
always @(posedge clk) begin always @(posedge clk) begin
if(resetEdge) $fwrite(file, "TRAIN\n"); if(resetEdge) $fwrite(file, "TRAIN\n");
if(Begin) $fwrite(file, "BEGIN %s\n", memfilename); if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
if(Enabled) begin if(Enabled) begin
$fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString); $fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString);
end end
if(dut.core.lsu.bus.dcache.dcache.cachefsm.FlushFlag) $fwrite(file, "0 F X\n"); if(dut.core.lsu.bus.dcache.dcache.cachefsm.FlushFlag) $fwrite(file, "0 F X\n");
if(EndSample) $fwrite(file, "END %s\n", memfilename); if(EndSample) $fwrite(file, "END %s\n", memfilename);
end end
end end
@ -642,45 +636,45 @@ end
if (`BPRED_LOGGER) begin if (`BPRED_LOGGER) begin
string direction; string direction;
int file; int file;
logic PCSrcM; logic PCSrcM;
string LogFile; string LogFile;
logic resetD, resetEdge; logic resetD, resetEdge;
flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
flop #(1) ResetDReg(clk, reset, resetD); flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD; assign resetEdge = ~reset & resetD;
initial begin initial begin
LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE); LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE);
file = $fopen(LogFile, "w"); file = $fopen(LogFile, "w");
end end
always @(posedge clk) begin always @(posedge clk) begin
if(resetEdge) $fwrite(file, "TRAIN\n"); if(resetEdge) $fwrite(file, "TRAIN\n");
if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
direction = PCSrcM ? "t" : "n"; direction = PCSrcM ? "t" : "n";
$fwrite(file, "%h %s\n", dut.core.PCM, direction); $fwrite(file, "%h %s\n", dut.core.PCM, direction);
end end
if(EndSample) $fwrite(file, "END %s\n", memfilename); if(EndSample) $fwrite(file, "END %s\n", memfilename);
end end
end end
end end
// check for hange up. // check for hang up.
logic [`XLEN-1:0] OldPCW; logic [`XLEN-1:0] OldPCW;
integer WatchDogTimerCount; integer WatchDogTimerCount;
localparam WatchDogTimerThreshold = 1000000; localparam WatchDogTimerThreshold = 1000000;
logic WatchDogTimeOut; logic WatchDogTimeOut;
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
OldPCW <= PCW; OldPCW <= PCW;
if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1; if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;
else WatchDogTimerCount = '0; else WatchDogTimerCount = '0;
end end
always_comb begin always_comb begin
WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold; WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
if(WatchDogTimeOut) begin if(WatchDogTimeOut) begin
$display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount); $display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
$stop; $stop;
end end
end end
endmodule endmodule
@ -698,34 +692,34 @@ module DCacheFlushFSM
logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)]; logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
if(`DCACHE_SUPPORTED) begin if(`DCACHE_SUPPORTED) begin
localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN; localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
localparam numwords = sramlen/`XLEN; localparam numwords = sramlen/`XLEN;
localparam lognumlines = $clog2(numlines); localparam lognumlines = $clog2(numlines);
localparam loglinebytelen = $clog2(linebytelen); localparam loglinebytelen = $clog2(linebytelen);
localparam lognumways = $clog2(numways); localparam lognumways = $clog2(numways);
localparam tagstart = lognumlines + loglinebytelen; localparam tagstart = lognumlines + loglinebytelen;
genvar index, way, cacheWord; genvar index, way, cacheWord;
logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
logic [sramlen-1:0] cacheline; logic [sramlen-1:0] cacheline;
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
for(index = 0; index < numlines; index++) begin for(index = 0; index < numlines; index++) begin
for(way = 0; way < numways; way++) begin for(way = 0; way < numways; way++) begin
for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
copyShadow #(.tagstart(tagstart), copyShadow #(.tagstart(tagstart),
.loglinebytelen(loglinebytelen), .sramlen(sramlen)) .loglinebytelen(loglinebytelen), .sramlen(sramlen))
copyShadow(.clk, copyShadow(.clk,
.start, .start,
.tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]), .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]),
.valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]), .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
@ -774,18 +768,18 @@ endmodule
module copyShadow module copyShadow
#(parameter tagstart, loglinebytelen, sramlen) #(parameter tagstart, loglinebytelen, sramlen)
(input logic clk, (input logic clk,
input logic start, input logic start,
input logic [`PA_BITS-1:tagstart] tag, input logic [`PA_BITS-1:tagstart] tag,
input logic valid, dirty, input logic valid, dirty,
input logic [sramlen-1:0] data, input logic [sramlen-1:0] data,
input logic [32-1:0] index, input logic [32-1:0] index,
input logic [32-1:0] cacheWord, input logic [32-1:0] cacheWord,
output logic [sramlen-1:0] CacheData, output logic [sramlen-1:0] CacheData,
output logic [`PA_BITS-1:0] CacheAdr, output logic [`PA_BITS-1:0] CacheAdr,
output logic [`XLEN-1:0] CacheTag, output logic [`XLEN-1:0] CacheTag,
output logic CacheValid, output logic CacheValid,
output logic CacheDirty); output logic CacheDirty);
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
@ -814,8 +808,7 @@ task automatic updateProgramAddrLabelArray;
integer returncode; integer returncode;
returncode = $fscanf(ProgramLabelMapFP, "%s\n", label); returncode = $fscanf(ProgramLabelMapFP, "%s\n", label);
returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr); returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
if (ProgramAddrLabelArray.exists(label)) if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
ProgramAddrLabelArray[label] = adrstr.atohex();
end end
end end
$fclose(ProgramLabelMapFP); $fclose(ProgramLabelMapFP);

3
testbench/tests.vh
View file

@ -52,7 +52,8 @@ string tvpaths[] = '{
"fpu", "fpu",
"lsu", "lsu",
"vm64check", "vm64check",
"pmp" "pmp",
"tlbKP"
}; };
string coremark[] = '{ string coremark[] = '{

3
tests/coverage/WALLY-init-lib.h
View file

@ -66,8 +66,7 @@ interrupt: # must be a timer interrupt
j trap_return # clean up and return j trap_return # clean up and return
exception: exception:
li t0, 2 csrr t0, mcause
csrr t1, mcause
li t1, 8 # is it an ecall trap? li t1, 8 # is it an ecall trap?
andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11 andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11
bne t0, t1, trap_return # ignore other exceptions bne t0, t1, trap_return # ignore other exceptions

48
tests/coverage/fpu.S
View file

@ -31,6 +31,44 @@ main:
#bseti t0, zero, 14 # turn on FPU #bseti t0, zero, 14 # turn on FPU
csrs mstatus, t0 csrs mstatus, t0
#Pull denormalized FP number from memory and pass it to fclass.S for coverage
la t0, TestData1
flw ft0, 0(t0)
fclass.s t1, ft0
#Result Sign Test Coverage
la t0, TestData2
flw ft0, 0(t0)
flw ft1, 4(t0)
fadd.s ft2, ft0, ft1 #Adds coverage for inf as arg for FADD
flw ft2, 4(t0)
fmsub.s ft3, ft0, ft1, ft2 #Adds coverage for fmaAs or Z Sign Bit
#Adds Coverage for Flag fmaAs, fmaPs, YSNaN, ZSNaN
fmadd.s ft3, ft0, ft1, ft2
flw ft0, 8(t0)
fmadd.s ft3, ft0, ft1, ft2
flw ft1, 12(t0)
fmadd.s ft3, ft0, ft1, ft2
flw ft2, 12(t0)
flw ft1, 4(t0)
fmadd.s ft3, ft0, ft1, ft2
#Add Coverage for round lsbRes
flw ft0, 16(t0)
flw ft1, 4(t0)
fmadd.s ft3, ft0, ft1, ft2
#Fix BadNaNBox test on unpackinput Z
la t0, TestData2
flw ft3, 0(t0)
flw ft4, 0(t0)
fadd.s ft5, ft3, ft4
# Test legal instructions not covered elsewhere # Test legal instructions not covered elsewhere
flq ft0, 0(a0) flq ft0, 0(a0)
flh ft0, 8(a0) flh ft0, 8(a0)
@ -98,3 +136,13 @@ main:
j done j done
.section .data
.align 3
TestData1:
.int 0x00100000 #Denormalized FP number
TestData2:
.int 0x3f800000 #FP 1.0
.word 0x7f800000 #INF
.int 0xbf800000 #FP -1.0
.int 0x7fa00000 #SNaN
.int 0x3fffffff #OverFlow Test

2
tests/coverage/lsu.S
View file

@ -30,4 +30,4 @@ main:
sfence.vma x0, x0 // sfence.vma to assert TLBFlush sfence.vma x0, x0 // sfence.vma to assert TLBFlush
j done j done

59
tests/coverage/priv.S
View file

@ -142,6 +142,65 @@ main:
# Test writes to floating point CSRs # Test writes to floating point CSRs
csrw frm, t0 csrw frm, t0
csrw fflags, t0 csrw fflags, t0
# CSRC MCOUNTEREN Register
# Go to machine mode
li a0, 3
ecall
# Activate HPM3
li t0, -1
csrw mcounteren, t0
csrw scounteren, t0
# Go to supervisor
li a0, 1
ecall
#try to write to HPMs
csrw 333, t0
#go to user mode
li a0, 0
ecall
csrr t0, hpmcounter22
# setting registers bits to 0
li a0, 3 # back to machine mode
ecall
li t0, 0
csrw mcounteren, t0
csrw scounteren, t0
# Write to satp when status.TVM is 1 from machine mode
bseti t0, zero, 20
csrs mstatus, t0
csrw satp, t0
# Test checking privilege for reading counters (using counter 22 as an example)
# Go to machine mode
li a0, 3
ecall
# Set SCOUNTEREN to all 0s, MCOUNTEREN to all 1s
li t0, 0
csrw scounteren, t0
li t1, -1
csrw mcounteren, t1
# Go to supervisor mode
li a0, 1
ecall
# try to read from HPM22
csrr t0, hpmcounter22
# go to user mode
li a0, 0
ecall
csrr t0, hpmcounter22
j done j done

143
tests/coverage/tlbKP.S Normal file
View file

@ -0,0 +1,143 @@
///////////////////////////////////////////
// lsu_test.S
//
// Written: mmendozamanriquez@hmc.edu 4 April 2023
// nlimpert@hmc.edu
//
// Purpose: Test coverage for LSU
//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// load code to initalize stack, handle interrupts, terminate
#include "WALLY-init-lib.h"
# run-elf.bash find this in project description
main:
# Page table root address at 0x80010000
li t5, 0x9000000000080010
csrw satp, t5
# sfence.vma x0, x0
# switch to supervisor mode
li a0, 1
ecall
li t0, 0x80015000
li t2, 0 # i = 0
li t3, 33 # Max amount of Loops = 32
loop: bge t2, t3, finished # exit loop if i >= loops
lw t1, 0(t0)
li t4, 0x1000
add t0, t0, t4
addi t2, t2, 1
j loop
finished:
j done
.data
.align 16
# Page table situated at 0x80010000
pagetable:
.8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong
.align 12
.8byte 0x0000000000000000
.8byte 0x00000000200048C1
.8byte 0x00000000200048C1
.align 12
.8byte 0x0000000020004CC1
//.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed?
.align 12
#80000000
.8byte 0x200000CF
.8byte 0x200004CF
.8byte 0x200008CF
.8byte 0x20000CCF
.8byte 0x200010CF
.8byte 0x200014CF
.8byte 0x200018CF
.8byte 0x20001CCF
.8byte 0x200020CF
.8byte 0x200024CF
.8byte 0x200028CF
.8byte 0x20002CCF
.8byte 0x200030CF
.8byte 0x200034CF
.8byte 0x200038CF
.8byte 0x20003CCF
.8byte 0x200040CF
.8byte 0x200044CF
.8byte 0x200048CF
.8byte 0x20004CCF
.8byte 0x200050CF
.8byte 0x200054CF
.8byte 0x200058CF
.8byte 0x20005CCF
.8byte 0x200060CF
.8byte 0x200064CF
.8byte 0x200068CF
.8byte 0x20006CCF
.8byte 0x200070CF
.8byte 0x200074CF
.8byte 0x200078CF
.8byte 0x20007CCF
.8byte 0x200080CF
.8byte 0x200084CF
.8byte 0x200088CF
.8byte 0x20008CCF
.8byte 0x200090CF
.8byte 0x200094CF
.8byte 0x200098CF
.8byte 0x20009CCF
.8byte 0x200100CF
.8byte 0x200104CF
.8byte 0x200108CF
.8byte 0x20010CCF
.8byte 0x200110CF
.8byte 0x200114CF
.8byte 0x200118CF
.8byte 0x20011CCF
.8byte 0x200120CF
.8byte 0x200124CF
.8byte 0x200128CF
.8byte 0x20012CCF
.8byte 0x200130CF
.8byte 0x200134CF