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https://github.com/openhwgroup/cvw.git
synced 2025-04-22 12:57:23 -04:00
Added sd_cmd and utility SPI functions.
This commit is contained in:
Jacob Pease
parent
c50df29e58
commit
ef1f55626c
4 changed files with 164 additions and 51 deletions
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@ -12,6 +12,7 @@ uint8_t crc7(uint8_t prev, uint8_t in) {
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return remainder & 0xff;
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}
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// Need to check this. This could be wrong as well.
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uint16_t crc16(uint16_t crc, uint8_t data) {
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// CRC polynomial 0x11021
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crc = (uint8_t)(crc >> 8) | (crc << 8);
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@ -22,13 +23,74 @@ uint16_t crc16(uint16_t crc, uint8_t data) {
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return crc;
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}
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uint8_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) {
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spi_send_byte
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uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) {
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uint8_t response_len;
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uint8_t i;
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uint64_t r;
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uint8_t rbyte;
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switch (cmd) {
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case 0:
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response_len = 1;
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break;
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case 8:
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response_len = 7
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break;
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default:
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response_len = 1;
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break;
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}
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// Make interrupt pending after response fifo receives the correct
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// response length.
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write_reg(SPI_RXMARK, response_len);
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// Write all 6 bytes into transfer fifo
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spi_sendbyte(0x40 | cmd);
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spi_sendbyte(arg >> 24);
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spi_sendbyte(arg >> 16);
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spi_sendbyte(arg >> 8);
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spi_sendbyte(arg);
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spi_sendbyte(crc);
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// Wait for command to send
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// The Transfer IP bit should go high when the txFIFO is empty
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// while(!(read_reg(SPI_IP) & 1)) {}
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waittx();
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// Read the dummy rxFIFO entries to move the head back to the tail
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for (i = 0; i < 6; i++) {
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spi_readbyte();
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}
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// Send "dummy signals". Since SPI is duplex,
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// useless bytes must be transferred
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for (i = 0; i < response_len; i++) {
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spi_sendbyte(0xFF);
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}
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// Wait for transfer fifo again
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waittx();
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// Read rxfifo response
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for (i = 0; i < response_len; i++) {
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rbyte = spi_readbyte();
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r = r | (rbyte << ((response_len - 1 - i)*8));
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}
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return r;
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}
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#define cmd0() sd_cmd( 0, 0x00000000, 0x95)
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#define cmd8() sd_cmd( 8, 0x000001aa, 0x87)
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// CMD55 has to be sent before ACMD41 (it means the next command is
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// application specific)
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#define cmd55() sd_cmd(55, 0x00000000, 0x65)
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#defube acmd41() sd_cmd(41, 0x40000000, 0x77)
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void init_sd(){
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init_spi();
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cmd0()
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}
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@ -4,6 +4,5 @@
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uint8_t crc7(uint8_t prev, uint8_t in);
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uint16_t crc16(uint16_t crc, uint8_t data);
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uint8_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc);
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uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc);
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void init_sd();
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@ -1,50 +1,87 @@
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///////////////////////////////////////////////////////////////////////
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// spi.c
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//
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// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
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//
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// Purpose: SPI Controller API for bootloader
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//
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//
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the
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// “License”); you may not use this file except in compliance with the
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// License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work
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// distributed under the License is distributed on an “AS IS” BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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// implied. See the License for the specific language governing
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// permissions and limitations under the License.
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///////////////////////////////////////////////////////////////////////
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#include "spi.h"
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void write_reg(uintptr_t addr, uint32_t value) {
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// Write to a register
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inline void write_reg(uintptr_t addr, uint32_t value) {
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volatile uint32_t * loc = (volatile uint32_t *) addr;
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*loc = value;
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}
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void read_red(uintptr_t addr) {
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// Read a register
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inline void read_reg(uintptr_t addr) {
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return *(volatile uint32_t *) addr;
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}
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// Queues a single byte in the transfer fifo
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inline void spi_sendbyte(uint8_t byte) {
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// Write byte to transfer fifo
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write_reg(SPI_TXDATA, byte);
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}
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inline uint8_t spi_readbyte() {
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return read_reg(SPI_RXDATA);
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}
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inline void waittx() {
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while(!(read_reg(SPI_IP) & 1)) {}
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}
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inline void waitrx() {
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while(read_reg(SPI_IP) & 2)) {}
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}
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// Initialize Sifive FU540 based SPI Controller
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void spi_init() {
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// Disable interrupts by default
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// write_reg(SPI_IE, 0);
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// Enable interrupts
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write_reg(SPI_IE, 0x3);
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// Set TXMARK to 1. If the number of entries is < 1
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// IP's txwm field will go high.
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// Set RXMARK to 0. If the number of entries is > 0
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// IP's rwxm field will go high.
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write_reg(SPI_TXMARK, 1);
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write_reg(SPI_RXMARK, 0);
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// Set Delay 0 to default
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write_reg(SPI_DELAY0,
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SIFIVE_SPI_DELAY0_CSSCK(1) |
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SIFIVE_SPI_DELAY0_SCKCS(1));
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// Set Delay 1 to default
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write_reg(SPI_DELAY1,
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SIFIVE_SPI_DELAY1_INTERCS(1) |
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SIFIVE_SPI_DELAY1_INTERXFR(0));
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// Initialize the SPI controller clock to
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// div = (20MHz/(2*400kHz)) - 1 = 24 = 0x18
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write_reg(SPI_SCKDIV, 0x18);
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}
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// Sends and receives a single byte
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uint8_t spi_send_byte(uint8_t byte) {
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// Write byte to transfer fifo
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write_reg(SPI_TXDATA, byte);
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/* Not sure how necessary this is. Will keep commented for now.
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// Wait a decent amount of time for data to send
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for (int i = 0; i < 100; i++) {
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__asm__ volatile("nop");
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}
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*/
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// Wait for data to come into receive fifo
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while (read_reg(SPI_IP) != 2) {}
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// Read received data
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result = read_reg(SPI_RXDATA);
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// Return result
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return result;
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}
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@ -4,26 +4,28 @@
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#include <stdint.h>
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#define SPI_BASE 0x13000 /* Base address of SPI device used for SDC */
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/* register offsets */
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#define SPI_SCKDIV 0x00 /* Serial clock divisor */
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#define SPI_SCKMODE 0x04 /* Serial clock mode */
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#define SPI_CSID 0x10 /* Chip select ID */
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#define SPI_CSDEF 0x14 /* Chip select default */
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#define SPI_CSMODE 0x18 /* Chip select mode */
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#define SPI_DELAY0 0x28 /* Delay control 0 */
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#define SPI_DELAY1 0x2c /* Delay control 1 */
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#define SPI_FMT 0x40 /* Frame format */
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#define SPI_TXDATA 0x48 /* Tx FIFO data */
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#define SPI_RXDATA 0x4c /* Rx FIFO data */
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#define SPI_TXMARK 0x50 /* Tx FIFO [<35;39;29Mwatermark */
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#define SPI_RXMARK 0x54 /* Rx FIFO watermark */
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#define SPI_SCKDIV SPI_BASE + 0x00 /* Serial clock divisor */
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#define SPI_SCKMODE SPI_BASE + 0x04 /* Serial clock mode */
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#define SPI_CSID SPI_BASE + 0x10 /* Chip select ID */
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#define SPI_CSDEF SPI_BASE + 0x14 /* Chip select default */
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#define SPI_CSMODE SPI_BASE + 0x18 /* Chip select mode */
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#define SPI_DELAY0 SPI_BASE + 0x28 /* Delay control 0 */
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#define SPI_DELAY1 SPI_BASE + 0x2c /* Delay control 1 */
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#define SPI_FMT SPI_BASE + 0x40 /* Frame format */
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#define SPI_TXDATA SPI_BASE + 0x48 /* Tx FIFO data */
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#define SPI_RXDATA SPI_BASE + 0x4c /* Rx FIFO data */
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#define SPI_TXMARK SPI_BASE + 0x50 /* Tx FIFO [<35;39;29Mwatermark */
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#define SPI_RXMARK SPI_BASE + 0x54 /* Rx FIFO watermark */
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/* Non-implemented
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#define SPI_FCTRL 0x60 // SPI flash interface control
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#define SPI_FFMT 0x64 // SPI flash instruction format
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#define SPI_FCTRL SPI_BASE + 0x60 // SPI flash interface control
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#define SPI_FFMT SPI_BASE + 0x64 // SPI flash instruction format
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*/
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#define SPI_IE 0x70 /* Interrupt Enable Register */
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#define SPI_IP 0x74 /* Interrupt Pendings Register */
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#define SPI_IE SPI_BASE + 0x70 /* Interrupt Enable Register */
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#define SPI_IP SPI_BASE + 0x74 /* Interrupt Pendings Register */
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/* delay0 bits */
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#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
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@ -37,9 +39,22 @@
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#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
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#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
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void write_reg(uintptr_t addr, uint32_t value);
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uint32_t read_reg(uintptr_t addr);
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uint8_t spi_send_byte(uint8_t byte);
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/* csmode bits */
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#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
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#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
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#define SIFIVE_SPI_CSMODE_MODE_OFF 3U
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#define WAITTX while(!(read_reg(SPI_IP) & 1) {}
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#define WAITRX while(read_reg(SPI_IP) & 2) {}
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inline void write_reg(uintptr_t addr, uint32_t value);
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inline uint32_t read_reg(uintptr_t addr);
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inline void spi_sendbyte(uint8_t byte);
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inline void waittx();
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inline void waitrx();
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uint8_t spi_txrx(uint8_t byte);
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inline uint8_t spi_readbyte();
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void spi_init();
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