mirror of
https://github.com/openhwgroup/cvw.git
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
David Harris
commit
eff9cec415
15 changed files with 249 additions and 1229 deletions
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@ -17,23 +17,23 @@ endgroup
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connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
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set_property port_width 64 [get_debug_ports u_ila_0/probe0]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
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connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/HWDATA[0]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[1]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[2]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[3]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[4]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[5]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[6]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[7]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[8]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[9]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[10]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[11]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[12]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[13]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[14]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[15]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[16]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[17]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[18]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[19]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[20]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[21]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[22]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[23]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[24]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[25]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[26]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[27]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[28]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[29]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[30]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[31]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[32]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[33]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[34]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[35]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[36]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[37]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[38]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[39]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[40]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[41]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[42]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[43]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[44]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[45]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[46]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[47]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[48]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[49]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[50]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[51]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[52]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[53]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[54]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[55]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[56]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[57]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[58]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[59]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[60]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[61]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[62]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[63]} ]]
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connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[0]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[1]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[2]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[3]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[4]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[5]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[6]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[7]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[8]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[9]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[10]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[11]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[12]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[13]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[14]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[15]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[16]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[17]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[18]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[19]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[20]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[21]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[22]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[23]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[24]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[25]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[26]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[27]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[28]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[29]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[30]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[31]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[32]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[33]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[34]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[35]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[36]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[37]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[38]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[39]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[40]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[41]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[42]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[43]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[44]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[45]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[46]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[47]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[48]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[49]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[50]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[51]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[52]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[53]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[54]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[55]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[56]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[57]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[58]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[59]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[60]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[61]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[62]} {wallypipelinedsoc/hart/lsu/LsuBusHWDATA[63]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 64 [get_debug_ports u_ila_0/probe1]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
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connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/HRDATA[0]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[1]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[2]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[3]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[4]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[5]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[6]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[7]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[8]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[9]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[10]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[11]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[12]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[13]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[14]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[15]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[16]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[17]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[18]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[19]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[20]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[21]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[22]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[23]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[24]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[25]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[26]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[27]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[28]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[29]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[30]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[31]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[32]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[33]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[34]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[35]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[36]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[37]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[38]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[39]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[40]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[41]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[42]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[43]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[44]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[45]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[46]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[47]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[48]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[49]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[50]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[51]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[52]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[53]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[54]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[55]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[56]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[57]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[58]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[59]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[60]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[61]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[62]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[63]} ]]
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connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[0]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[1]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[2]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[3]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[4]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[5]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[6]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[7]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[8]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[9]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[10]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[11]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[12]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[13]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[14]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[15]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[16]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[17]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[18]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[19]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[20]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[21]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[22]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[23]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[24]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[25]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[26]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[27]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[28]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[29]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[30]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[31]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[32]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[33]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[34]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[35]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[36]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[37]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[38]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[39]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[40]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[41]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[42]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[43]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[44]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[45]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[46]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[47]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[48]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[49]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[50]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[51]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[52]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[53]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[54]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[55]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[56]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[57]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[58]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[59]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[60]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[61]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[62]} {wallypipelinedsoc/hart/lsu/LsuBusHRDATA[63]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 32 [get_debug_ports u_ila_0/probe2]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
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connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[0]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[1]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[2]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[3]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[4]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[5]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[6]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[7]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[8]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[9]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[10]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[11]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[12]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[13]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[14]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[15]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[16]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[17]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[18]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[19]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[20]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[21]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[22]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[23]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[24]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[25]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[26]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[27]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[28]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[29]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[30]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[31]} ]]
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connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/hart/lsu/LsuBusAdr[0]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[1]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[2]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[3]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[4]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[5]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[6]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[7]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[8]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[9]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[10]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[11]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[12]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[13]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[14]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[15]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[16]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[17]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[18]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[19]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[20]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[21]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[22]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[23]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[24]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[25]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[26]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[27]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[28]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[29]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[30]} {wallypipelinedsoc/hart/lsu/LsuBusAdr[31]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 6 [get_debug_ports u_ila_0/probe3]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
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connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MIP_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[11]} ]]
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connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsoc/hart/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsoc/hart/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsoc/hart/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsoc/hart/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsoc/hart/priv.priv/trap/MIP_REGW[11]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 64 [get_debug_ports u_ila_0/probe4]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[63]} ]]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe5]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
|
|
@ -62,15 +62,15 @@ connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/hart/MemRW
|
|||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe11]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[11]} ]]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIE_REGW[11]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe12]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[63]} ]]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[63]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe13]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[11]} ]]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIP_REGW[11]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 5 [get_debug_ports u_ila_0/probe14]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||
|
|
@ -86,31 +86,31 @@ connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/uncore/sdc
|
|||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe17]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[0]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[1]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[2]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[3]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[4]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[5]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[6]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[7]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[8]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[9]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[10]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[11]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[12]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[13]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[14]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[15]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[16]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[17]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[18]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[19]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[20]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[21]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[22]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[23]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[24]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[25]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[26]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[27]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[28]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[29]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[30]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[31]} ]]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[3]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[4]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[5]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[6]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[7]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[8]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[9]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[10]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[11]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[12]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[13]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[14]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[15]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[16]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[17]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[18]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[19]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[20]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[21]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[22]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[23]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[24]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[25]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[26]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[27]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[28]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[29]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[30]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[31]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe18]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[63]} ]]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[63]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe19]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[63]} ]]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SCAUSE_REGW[63]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe20]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[63]} ]]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[63]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe21]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
||||
connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SIP_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SIP_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SIP_REGW[9]} ]]
|
||||
connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/SIP_REGW[1]} {wallypipelinedsoc/hart/priv.priv/trap/SIP_REGW[5]} {wallypipelinedsoc/hart/priv.priv/trap/SIP_REGW[9]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe22]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SIE_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SIE_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SIE_REGW[9]} ]]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/SIE_REGW[1]} {wallypipelinedsoc/hart/priv.priv/trap/SIE_REGW[5]} {wallypipelinedsoc/hart/priv.priv/trap/SIE_REGW[9]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 63 [get_debug_ports u_ila_0/probe23]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
||||
connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[63]} ]]
|
||||
connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[0]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[2]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[3]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[4]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[5]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[6]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[7]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[8]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[9]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[10]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[11]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[12]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[13]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[14]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[15]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[16]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[17]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[18]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[19]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[20]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[21]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[22]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[23]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[24]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[25]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[26]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[27]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[28]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[29]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[30]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[31]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[32]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[33]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[34]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[35]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[36]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[37]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[38]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[39]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[40]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[41]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[42]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[43]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[44]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[45]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[46]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[47]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[48]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[49]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[50]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[51]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[52]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[53]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[54]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[55]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[56]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[57]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[58]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[59]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[60]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[61]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[62]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[63]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe24]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
||||
|
|
@ -122,15 +122,15 @@ connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncore/sdc
|
|||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 12 [get_debug_ports u_ila_0/probe26]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
||||
connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/hart/priv/trap/PendingIntsM[0]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[1]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[2]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[3]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[4]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[5]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[6]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[7]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[8]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[9]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[10]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[11]} ]]
|
||||
connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[0]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[1]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[2]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[3]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[4]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[5]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[6]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[7]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[8]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[9]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[10]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[11]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe27]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
||||
connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[63]} ]]
|
||||
connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[63]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe28]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
||||
connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MIE_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[11]} ]]
|
||||
connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsoc/hart/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsoc/hart/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsoc/hart/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsoc/hart/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsoc/hart/priv.priv/trap/MIE_REGW[11]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe29]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
||||
|
|
@ -142,23 +142,23 @@ connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncore/sdc
|
|||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe31]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
||||
connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[0]} {wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[1]} ]]
|
||||
connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/hart/lsu/LsuBusSize[0]} {wallypipelinedsoc/hart/lsu/LsuBusSize[1]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
||||
connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBAck ]]
|
||||
connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/hart/lsu/LsuBusAck ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
||||
connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBRead ]]
|
||||
connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/hart/lsu/LsuBusRead ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
||||
connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBWrite ]]
|
||||
connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/hart/lsu/LsuBusWrite ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
||||
connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/hart/priv/trap/BreakpointFaultM ]]
|
||||
connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/BreakpointFaultM ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
||||
|
|
@ -166,7 +166,7 @@ connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/uncore/uart
|
|||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
|
||||
connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/hart/priv/trap/EcallFaultM ]]
|
||||
connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/EcallFaultM ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
|
||||
|
|
@ -186,15 +186,15 @@ connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/uncore/sdc.
|
|||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
|
||||
connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/hart/priv/trap/IllegalInstrFaultM ]]
|
||||
connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/IllegalInstrFaultM ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
|
||||
connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/hart/priv/trap/InstrAccessFaultM ]]
|
||||
connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/InstrAccessFaultM ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
|
||||
connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/hart/priv/trap/InstrPageFaultM ]]
|
||||
connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/InstrPageFaultM ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
|
||||
|
|
@ -206,19 +206,19 @@ connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/uncore/uart
|
|||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
|
||||
connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadAccessFaultM ]]
|
||||
connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/LoadAccessFaultM ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
|
||||
connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadMisalignedFaultM ]]
|
||||
connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/LoadMisalignedFaultM ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
|
||||
connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadPageFaultM ]]
|
||||
connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/LoadPageFaultM ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
|
||||
connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/hart/priv/trap/mretM ]]
|
||||
connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/mretM ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
|
||||
|
|
@ -270,19 +270,19 @@ connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/uncore/uart
|
|||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe63]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
|
||||
connect_debug_port u_ila_0/probe63 [get_nets [list wallypipelinedsoc/hart/priv/trap/sretM ]]
|
||||
connect_debug_port u_ila_0/probe63 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/sretM ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
|
||||
connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/hart/priv/trap/StoreAccessFaultM ]]
|
||||
connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/StoreAccessFaultM ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe65]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
|
||||
connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/hart/priv/trap/StoreMisalignedFaultM ]]
|
||||
connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/StoreMisalignedFaultM ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe66]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
|
||||
connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/hart/priv/trap/StorePageFaultM ]]
|
||||
connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/StorePageFaultM ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe67]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
|
||||
|
|
@ -446,44 +446,45 @@ connect_debug_port u_ila_0/probe98 [get_nets [list wallypipelinedsoc/hart/hzu/Fl
|
|||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 24 [get_debug_ports u_ila_0/probe99]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
|
||||
connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[0]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[1]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[2]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[3]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[4]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[5]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[6]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[7]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[8]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[9]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[10]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[11]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[12]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[13]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[14]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[15]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[16]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[17]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[18]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[19]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[20]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[21]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[22]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[23]}]]
|
||||
connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[3]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[4]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[5]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[6]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[7]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[8]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[9]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[10]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[11]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[12]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[13]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[14]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[15]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[16]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[17]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[18]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[19]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[20]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[21]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[22]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[23]}]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe100]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100]
|
||||
connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/hart/ifu/icache/InstrInF[0]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[1]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[2]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[3]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[4]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[5]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[6]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[7]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[8]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[9]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[10]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[11]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[12]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[13]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[14]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[15]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[16]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[17]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[18]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[19]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[20]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[21]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[22]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[23]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[24]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[25]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[26]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[27]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[28]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[29]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[30]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[31]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[32]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[33]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[34]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[35]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[36]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[37]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[38]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[39]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[40]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[41]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[42]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[43]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[44]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[45]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[46]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[47]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[48]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[49]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[50]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[51]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[52]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[53]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[54]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[55]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[56]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[57]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[58]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[59]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[60]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[61]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[62]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[63]}]]
|
||||
connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[0]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[1]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[2]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[3]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[4]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[5]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[6]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[7]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[8]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[9]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[10]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[11]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[12]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[13]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[14]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[15]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[16]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[17]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[18]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[19]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[20]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[21]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[22]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[23]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[24]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[25]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[26]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[27]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[28]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[29]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[30]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[31]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[32]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[33]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[34]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[35]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[36]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[37]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[38]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[39]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[40]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[41]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[42]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[43]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[44]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[45]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[46]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[47]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[48]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[49]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[50]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[51]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[52]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[53]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[54]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[55]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[56]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[57]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[58]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[59]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[60]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[61]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[62]} {wallypipelinedsoc/hart/ifu/IfuBusHRDATA[63]}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe101]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101]
|
||||
connect_debug_port u_ila_0/probe101 [get_nets [list wallypipelinedsoc/hart/ifu/icache/InstrAckF ]]
|
||||
connect_debug_port u_ila_0/probe101 [get_nets [list wallypipelinedsoc/hart/ifu/IfuBusAck ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe102]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102]
|
||||
connect_debug_port u_ila_0/probe102 [get_nets [list {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[0]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[1]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[2]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[3]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[4]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[5]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[6]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[7]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[8]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[9]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[10]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[11]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[12]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[13]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[14]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[15]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[16]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[17]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[18]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[19]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[20]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[21]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[22]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[23]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[24]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[25]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[26]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[27]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[28]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[29]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[30]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[31]}]]
|
||||
connect_debug_port u_ila_0/probe102 [get_nets [list {wallypipelinedsoc/hart/ifu/IfuBusAdr[0]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[1]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[2]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[3]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[4]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[5]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[6]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[7]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[8]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[9]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[10]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[11]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[12]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[13]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[14]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[15]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[16]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[17]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[18]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[19]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[20]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[21]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[22]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[23]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[24]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[25]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[26]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[27]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[28]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[29]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[30]} {wallypipelinedsoc/hart/ifu/IfuBusAdr[31]}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe103]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103]
|
||||
connect_debug_port u_ila_0/probe103 [get_nets [list wallypipelinedsoc/hart/ifu/icache/InstrReadF ]]
|
||||
connect_debug_port u_ila_0/probe103 [get_nets [list wallypipelinedsoc/hart/ifu/IfuBusRead ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe104]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104]
|
||||
connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[0]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[1]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[2]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[3]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[4]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[5]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[6]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[7]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[8]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[9]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[10]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[11]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[12]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[13]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[14]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[15]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[16]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[17]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[18]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[19]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[20]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[21]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[22]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[23]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[24]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[25]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[26]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[27]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[28]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[29]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[30]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[31]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[32]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[33]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[34]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[35]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[36]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[37]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[38]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[39]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[40]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[41]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[42]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[43]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[44]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[45]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[46]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[47]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[48]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[49]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[50]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[51]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[52]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[53]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[54]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[55]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[56]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[57]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[58]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[59]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[60]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[61]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[62]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[63]}]]
|
||||
connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/counters/INSTRET_REGW[63]}]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe105]
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe105]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105]
|
||||
connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/hart/ebu/HRDATA[0]} {wallypipelinedsoc/hart/ebu/HRDATA[1]} {wallypipelinedsoc/hart/ebu/HRDATA[2]} {wallypipelinedsoc/hart/ebu/HRDATA[3]} {wallypipelinedsoc/hart/ebu/HRDATA[4]} {wallypipelinedsoc/hart/ebu/HRDATA[5]} {wallypipelinedsoc/hart/ebu/HRDATA[6]} {wallypipelinedsoc/hart/ebu/HRDATA[7]} {wallypipelinedsoc/hart/ebu/HRDATA[8]} {wallypipelinedsoc/hart/ebu/HRDATA[9]} {wallypipelinedsoc/hart/ebu/HRDATA[10]} {wallypipelinedsoc/hart/ebu/HRDATA[11]} {wallypipelinedsoc/hart/ebu/HRDATA[12]} {wallypipelinedsoc/hart/ebu/HRDATA[13]} {wallypipelinedsoc/hart/ebu/HRDATA[14]} {wallypipelinedsoc/hart/ebu/HRDATA[15]} {wallypipelinedsoc/hart/ebu/HRDATA[16]} {wallypipelinedsoc/hart/ebu/HRDATA[17]} {wallypipelinedsoc/hart/ebu/HRDATA[18]} {wallypipelinedsoc/hart/ebu/HRDATA[19]} {wallypipelinedsoc/hart/ebu/HRDATA[20]} {wallypipelinedsoc/hart/ebu/HRDATA[21]} {wallypipelinedsoc/hart/ebu/HRDATA[22]} {wallypipelinedsoc/hart/ebu/HRDATA[23]} {wallypipelinedsoc/hart/ebu/HRDATA[24]} {wallypipelinedsoc/hart/ebu/HRDATA[25]} {wallypipelinedsoc/hart/ebu/HRDATA[26]} {wallypipelinedsoc/hart/ebu/HRDATA[27]} {wallypipelinedsoc/hart/ebu/HRDATA[28]} {wallypipelinedsoc/hart/ebu/HRDATA[29]} {wallypipelinedsoc/hart/ebu/HRDATA[30]} {wallypipelinedsoc/hart/ebu/HRDATA[31]}]]
|
||||
connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/hart/ebu/HRDATA[0]} {wallypipelinedsoc/hart/ebu/HRDATA[1]} {wallypipelinedsoc/hart/ebu/HRDATA[2]} {wallypipelinedsoc/hart/ebu/HRDATA[3]} {wallypipelinedsoc/hart/ebu/HRDATA[4]} {wallypipelinedsoc/hart/ebu/HRDATA[5]} {wallypipelinedsoc/hart/ebu/HRDATA[6]} {wallypipelinedsoc/hart/ebu/HRDATA[7]} {wallypipelinedsoc/hart/ebu/HRDATA[8]} {wallypipelinedsoc/hart/ebu/HRDATA[9]} {wallypipelinedsoc/hart/ebu/HRDATA[10]} {wallypipelinedsoc/hart/ebu/HRDATA[11]} {wallypipelinedsoc/hart/ebu/HRDATA[12]} {wallypipelinedsoc/hart/ebu/HRDATA[13]} {wallypipelinedsoc/hart/ebu/HRDATA[14]} {wallypipelinedsoc/hart/ebu/HRDATA[15]} {wallypipelinedsoc/hart/ebu/HRDATA[16]} {wallypipelinedsoc/hart/ebu/HRDATA[17]} {wallypipelinedsoc/hart/ebu/HRDATA[18]} {wallypipelinedsoc/hart/ebu/HRDATA[19]} {wallypipelinedsoc/hart/ebu/HRDATA[20]} {wallypipelinedsoc/hart/ebu/HRDATA[21]} {wallypipelinedsoc/hart/ebu/HRDATA[22]} {wallypipelinedsoc/hart/ebu/HRDATA[23]} {wallypipelinedsoc/hart/ebu/HRDATA[24]} {wallypipelinedsoc/hart/ebu/HRDATA[25]} {wallypipelinedsoc/hart/ebu/HRDATA[26]} {wallypipelinedsoc/hart/ebu/HRDATA[27]} {wallypipelinedsoc/hart/ebu/HRDATA[28]} {wallypipelinedsoc/hart/ebu/HRDATA[29]} {wallypipelinedsoc/hart/ebu/HRDATA[30]} {wallypipelinedsoc/hart/ebu/HRDATA[31]} {wallypipelinedsoc/hart/ebu/HRDATA[32]} {wallypipelinedsoc/hart/ebu/HRDATA[33]} {wallypipelinedsoc/hart/ebu/HRDATA[34]} {wallypipelinedsoc/hart/ebu/HRDATA[35]} {wallypipelinedsoc/hart/ebu/HRDATA[36]} {wallypipelinedsoc/hart/ebu/HRDATA[37]} {wallypipelinedsoc/hart/ebu/HRDATA[38]} {wallypipelinedsoc/hart/ebu/HRDATA[39]} {wallypipelinedsoc/hart/ebu/HRDATA[40]} {wallypipelinedsoc/hart/ebu/HRDATA[41]} {wallypipelinedsoc/hart/ebu/HRDATA[42]} {wallypipelinedsoc/hart/ebu/HRDATA[43]} {wallypipelinedsoc/hart/ebu/HRDATA[44]} {wallypipelinedsoc/hart/ebu/HRDATA[45]} {wallypipelinedsoc/hart/ebu/HRDATA[46]} {wallypipelinedsoc/hart/ebu/HRDATA[47]} {wallypipelinedsoc/hart/ebu/HRDATA[48]} {wallypipelinedsoc/hart/ebu/HRDATA[49]} {wallypipelinedsoc/hart/ebu/HRDATA[50]} {wallypipelinedsoc/hart/ebu/HRDATA[51]} {wallypipelinedsoc/hart/ebu/HRDATA[52]} {wallypipelinedsoc/hart/ebu/HRDATA[53]} {wallypipelinedsoc/hart/ebu/HRDATA[54]} {wallypipelinedsoc/hart/ebu/HRDATA[55]} {wallypipelinedsoc/hart/ebu/HRDATA[56]} {wallypipelinedsoc/hart/ebu/HRDATA[57]} {wallypipelinedsoc/hart/ebu/HRDATA[58]} {wallypipelinedsoc/hart/ebu/HRDATA[59]} {wallypipelinedsoc/hart/ebu/HRDATA[60]} {wallypipelinedsoc/hart/ebu/HRDATA[61]} {wallypipelinedsoc/hart/ebu/HRDATA[62]} {wallypipelinedsoc/hart/ebu/HRDATA[63]}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe106]
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe106]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe106]
|
||||
connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/hart/ebu/HWDATA[0]} {wallypipelinedsoc/hart/ebu/HWDATA[1]} {wallypipelinedsoc/hart/ebu/HWDATA[2]} {wallypipelinedsoc/hart/ebu/HWDATA[3]} {wallypipelinedsoc/hart/ebu/HWDATA[4]} {wallypipelinedsoc/hart/ebu/HWDATA[5]} {wallypipelinedsoc/hart/ebu/HWDATA[6]} {wallypipelinedsoc/hart/ebu/HWDATA[7]} {wallypipelinedsoc/hart/ebu/HWDATA[8]} {wallypipelinedsoc/hart/ebu/HWDATA[9]} {wallypipelinedsoc/hart/ebu/HWDATA[10]} {wallypipelinedsoc/hart/ebu/HWDATA[11]} {wallypipelinedsoc/hart/ebu/HWDATA[12]} {wallypipelinedsoc/hart/ebu/HWDATA[13]} {wallypipelinedsoc/hart/ebu/HWDATA[14]} {wallypipelinedsoc/hart/ebu/HWDATA[15]} {wallypipelinedsoc/hart/ebu/HWDATA[16]} {wallypipelinedsoc/hart/ebu/HWDATA[17]} {wallypipelinedsoc/hart/ebu/HWDATA[18]} {wallypipelinedsoc/hart/ebu/HWDATA[19]} {wallypipelinedsoc/hart/ebu/HWDATA[20]} {wallypipelinedsoc/hart/ebu/HWDATA[21]} {wallypipelinedsoc/hart/ebu/HWDATA[22]} {wallypipelinedsoc/hart/ebu/HWDATA[23]} {wallypipelinedsoc/hart/ebu/HWDATA[24]} {wallypipelinedsoc/hart/ebu/HWDATA[25]} {wallypipelinedsoc/hart/ebu/HWDATA[26]} {wallypipelinedsoc/hart/ebu/HWDATA[27]} {wallypipelinedsoc/hart/ebu/HWDATA[28]} {wallypipelinedsoc/hart/ebu/HWDATA[29]} {wallypipelinedsoc/hart/ebu/HWDATA[30]} {wallypipelinedsoc/hart/ebu/HWDATA[31]}]]
|
||||
connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/hart/ebu/HWDATA[0]} {wallypipelinedsoc/hart/ebu/HWDATA[1]} {wallypipelinedsoc/hart/ebu/HWDATA[2]} {wallypipelinedsoc/hart/ebu/HWDATA[3]} {wallypipelinedsoc/hart/ebu/HWDATA[4]} {wallypipelinedsoc/hart/ebu/HWDATA[5]} {wallypipelinedsoc/hart/ebu/HWDATA[6]} {wallypipelinedsoc/hart/ebu/HWDATA[7]} {wallypipelinedsoc/hart/ebu/HWDATA[8]} {wallypipelinedsoc/hart/ebu/HWDATA[9]} {wallypipelinedsoc/hart/ebu/HWDATA[10]} {wallypipelinedsoc/hart/ebu/HWDATA[11]} {wallypipelinedsoc/hart/ebu/HWDATA[12]} {wallypipelinedsoc/hart/ebu/HWDATA[13]} {wallypipelinedsoc/hart/ebu/HWDATA[14]} {wallypipelinedsoc/hart/ebu/HWDATA[15]} {wallypipelinedsoc/hart/ebu/HWDATA[16]} {wallypipelinedsoc/hart/ebu/HWDATA[17]} {wallypipelinedsoc/hart/ebu/HWDATA[18]} {wallypipelinedsoc/hart/ebu/HWDATA[19]} {wallypipelinedsoc/hart/ebu/HWDATA[20]} {wallypipelinedsoc/hart/ebu/HWDATA[21]} {wallypipelinedsoc/hart/ebu/HWDATA[22]} {wallypipelinedsoc/hart/ebu/HWDATA[23]} {wallypipelinedsoc/hart/ebu/HWDATA[24]} {wallypipelinedsoc/hart/ebu/HWDATA[25]} {wallypipelinedsoc/hart/ebu/HWDATA[26]} {wallypipelinedsoc/hart/ebu/HWDATA[27]} {wallypipelinedsoc/hart/ebu/HWDATA[28]} {wallypipelinedsoc/hart/ebu/HWDATA[29]} {wallypipelinedsoc/hart/ebu/HWDATA[30]} {wallypipelinedsoc/hart/ebu/HWDATA[31]} {wallypipelinedsoc/hart/ebu/HWDATA[32]} {wallypipelinedsoc/hart/ebu/HWDATA[33]} {wallypipelinedsoc/hart/ebu/HWDATA[34]} {wallypipelinedsoc/hart/ebu/HWDATA[35]} {wallypipelinedsoc/hart/ebu/HWDATA[36]} {wallypipelinedsoc/hart/ebu/HWDATA[37]} {wallypipelinedsoc/hart/ebu/HWDATA[38]} {wallypipelinedsoc/hart/ebu/HWDATA[39]} {wallypipelinedsoc/hart/ebu/HWDATA[40]} {wallypipelinedsoc/hart/ebu/HWDATA[41]} {wallypipelinedsoc/hart/ebu/HWDATA[42]} {wallypipelinedsoc/hart/ebu/HWDATA[43]} {wallypipelinedsoc/hart/ebu/HWDATA[44]} {wallypipelinedsoc/hart/ebu/HWDATA[45]} {wallypipelinedsoc/hart/ebu/HWDATA[46]} {wallypipelinedsoc/hart/ebu/HWDATA[47]} {wallypipelinedsoc/hart/ebu/HWDATA[48]} {wallypipelinedsoc/hart/ebu/HWDATA[49]} {wallypipelinedsoc/hart/ebu/HWDATA[50]} {wallypipelinedsoc/hart/ebu/HWDATA[51]} {wallypipelinedsoc/hart/ebu/HWDATA[52]} {wallypipelinedsoc/hart/ebu/HWDATA[53]} {wallypipelinedsoc/hart/ebu/HWDATA[54]} {wallypipelinedsoc/hart/ebu/HWDATA[55]} {wallypipelinedsoc/hart/ebu/HWDATA[56]} {wallypipelinedsoc/hart/ebu/HWDATA[57]} {wallypipelinedsoc/hart/ebu/HWDATA[58]} {wallypipelinedsoc/hart/ebu/HWDATA[59]} {wallypipelinedsoc/hart/ebu/HWDATA[60]} {wallypipelinedsoc/hart/ebu/HWDATA[61]} {wallypipelinedsoc/hart/ebu/HWDATA[62]} {wallypipelinedsoc/hart/ebu/HWDATA[63]}]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe107]
|
||||
|
|
@ -529,43 +530,43 @@ connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsoc/hart/ebu/
|
|||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe115]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe115]
|
||||
connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsoc/hart/priv/InterruptM}]]
|
||||
connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsoc/hart/priv.priv/InterruptM}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe116]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe116]
|
||||
connect_debug_port u_ila_0/probe116 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/ITLBMissF]]
|
||||
connect_debug_port u_ila_0/probe116 [get_nets [list wallypipelinedsoc/hart/lsu/ITLBMissF]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe117]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe117]
|
||||
connect_debug_port u_ila_0/probe117 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/DTLBMissM]]
|
||||
connect_debug_port u_ila_0/probe117 [get_nets [list wallypipelinedsoc/hart/lsu/DTLBMissM]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe118]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe118]
|
||||
connect_debug_port u_ila_0/probe118 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/ITLBWriteF]]
|
||||
connect_debug_port u_ila_0/probe118 [get_nets [list wallypipelinedsoc/hart/lsu/ITLBWriteF]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe119]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe119]
|
||||
connect_debug_port u_ila_0/probe119 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/DTLBWriteM]]
|
||||
connect_debug_port u_ila_0/probe119 [get_nets [list wallypipelinedsoc/hart/lsu/DTLBWriteM]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 11 [get_debug_ports u_ila_0/probe120]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120]
|
||||
connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/hart/lsu/hptw/WalkerState[0]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[1]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[2]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[3]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[4]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[5]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[6]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[7]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[8]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[9]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[10]}]]
|
||||
connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[0]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[1]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[2]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[3]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[4]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[5]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[6]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[7]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[8]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[9]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[10]}]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 56 [get_debug_ports u_ila_0/probe121]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe121]
|
||||
connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/hart/lsu/MemPAdrM[0]} {wallypipelinedsoc/hart/lsu/MemPAdrM[1]} {wallypipelinedsoc/hart/lsu/MemPAdrM[2]} {wallypipelinedsoc/hart/lsu/MemPAdrM[3]} {wallypipelinedsoc/hart/lsu/MemPAdrM[4]} {wallypipelinedsoc/hart/lsu/MemPAdrM[5]} {wallypipelinedsoc/hart/lsu/MemPAdrM[6]} {wallypipelinedsoc/hart/lsu/MemPAdrM[7]} {wallypipelinedsoc/hart/lsu/MemPAdrM[8]} {wallypipelinedsoc/hart/lsu/MemPAdrM[9]} {wallypipelinedsoc/hart/lsu/MemPAdrM[10]} {wallypipelinedsoc/hart/lsu/MemPAdrM[11]} {wallypipelinedsoc/hart/lsu/MemPAdrM[12]} {wallypipelinedsoc/hart/lsu/MemPAdrM[13]} {wallypipelinedsoc/hart/lsu/MemPAdrM[14]} {wallypipelinedsoc/hart/lsu/MemPAdrM[15]} {wallypipelinedsoc/hart/lsu/MemPAdrM[16]} {wallypipelinedsoc/hart/lsu/MemPAdrM[17]} {wallypipelinedsoc/hart/lsu/MemPAdrM[18]} {wallypipelinedsoc/hart/lsu/MemPAdrM[19]} {wallypipelinedsoc/hart/lsu/MemPAdrM[20]} {wallypipelinedsoc/hart/lsu/MemPAdrM[21]} {wallypipelinedsoc/hart/lsu/MemPAdrM[22]} {wallypipelinedsoc/hart/lsu/MemPAdrM[23]} {wallypipelinedsoc/hart/lsu/MemPAdrM[24]} {wallypipelinedsoc/hart/lsu/MemPAdrM[25]} {wallypipelinedsoc/hart/lsu/MemPAdrM[26]} {wallypipelinedsoc/hart/lsu/MemPAdrM[27]} {wallypipelinedsoc/hart/lsu/MemPAdrM[28]} {wallypipelinedsoc/hart/lsu/MemPAdrM[29]} {wallypipelinedsoc/hart/lsu/MemPAdrM[30]} {wallypipelinedsoc/hart/lsu/MemPAdrM[31]} {wallypipelinedsoc/hart/lsu/MemPAdrM[32]} {wallypipelinedsoc/hart/lsu/MemPAdrM[33]} {wallypipelinedsoc/hart/lsu/MemPAdrM[34]} {wallypipelinedsoc/hart/lsu/MemPAdrM[35]} {wallypipelinedsoc/hart/lsu/MemPAdrM[36]} {wallypipelinedsoc/hart/lsu/MemPAdrM[37]} {wallypipelinedsoc/hart/lsu/MemPAdrM[38]} {wallypipelinedsoc/hart/lsu/MemPAdrM[39]} {wallypipelinedsoc/hart/lsu/MemPAdrM[40]} {wallypipelinedsoc/hart/lsu/MemPAdrM[41]} {wallypipelinedsoc/hart/lsu/MemPAdrM[42]} {wallypipelinedsoc/hart/lsu/MemPAdrM[43]} {wallypipelinedsoc/hart/lsu/MemPAdrM[44]} {wallypipelinedsoc/hart/lsu/MemPAdrM[45]} {wallypipelinedsoc/hart/lsu/MemPAdrM[46]} {wallypipelinedsoc/hart/lsu/MemPAdrM[47]} {wallypipelinedsoc/hart/lsu/MemPAdrM[48]} {wallypipelinedsoc/hart/lsu/MemPAdrM[49]} {wallypipelinedsoc/hart/lsu/MemPAdrM[50]} {wallypipelinedsoc/hart/lsu/MemPAdrM[51]} {wallypipelinedsoc/hart/lsu/MemPAdrM[52]} {wallypipelinedsoc/hart/lsu/MemPAdrM[53]} {wallypipelinedsoc/hart/lsu/MemPAdrM[54]} {wallypipelinedsoc/hart/lsu/MemPAdrM[55]} ]]
|
||||
connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/hart/lsu/IEUAdrM[0]} {wallypipelinedsoc/hart/lsu/IEUAdrM[1]} {wallypipelinedsoc/hart/lsu/IEUAdrM[2]} {wallypipelinedsoc/hart/lsu/IEUAdrM[3]} {wallypipelinedsoc/hart/lsu/IEUAdrM[4]} {wallypipelinedsoc/hart/lsu/IEUAdrM[5]} {wallypipelinedsoc/hart/lsu/IEUAdrM[6]} {wallypipelinedsoc/hart/lsu/IEUAdrM[7]} {wallypipelinedsoc/hart/lsu/IEUAdrM[8]} {wallypipelinedsoc/hart/lsu/IEUAdrM[9]} {wallypipelinedsoc/hart/lsu/IEUAdrM[10]} {wallypipelinedsoc/hart/lsu/IEUAdrM[11]} {wallypipelinedsoc/hart/lsu/IEUAdrM[12]} {wallypipelinedsoc/hart/lsu/IEUAdrM[13]} {wallypipelinedsoc/hart/lsu/IEUAdrM[14]} {wallypipelinedsoc/hart/lsu/IEUAdrM[15]} {wallypipelinedsoc/hart/lsu/IEUAdrM[16]} {wallypipelinedsoc/hart/lsu/IEUAdrM[17]} {wallypipelinedsoc/hart/lsu/IEUAdrM[18]} {wallypipelinedsoc/hart/lsu/IEUAdrM[19]} {wallypipelinedsoc/hart/lsu/IEUAdrM[20]} {wallypipelinedsoc/hart/lsu/IEUAdrM[21]} {wallypipelinedsoc/hart/lsu/IEUAdrM[22]} {wallypipelinedsoc/hart/lsu/IEUAdrM[23]} {wallypipelinedsoc/hart/lsu/IEUAdrM[24]} {wallypipelinedsoc/hart/lsu/IEUAdrM[25]} {wallypipelinedsoc/hart/lsu/IEUAdrM[26]} {wallypipelinedsoc/hart/lsu/IEUAdrM[27]} {wallypipelinedsoc/hart/lsu/IEUAdrM[28]} {wallypipelinedsoc/hart/lsu/IEUAdrM[29]} {wallypipelinedsoc/hart/lsu/IEUAdrM[30]} {wallypipelinedsoc/hart/lsu/IEUAdrM[31]} {wallypipelinedsoc/hart/lsu/IEUAdrM[32]} {wallypipelinedsoc/hart/lsu/IEUAdrM[33]} {wallypipelinedsoc/hart/lsu/IEUAdrM[34]} {wallypipelinedsoc/hart/lsu/IEUAdrM[35]} {wallypipelinedsoc/hart/lsu/IEUAdrM[36]} {wallypipelinedsoc/hart/lsu/IEUAdrM[37]} {wallypipelinedsoc/hart/lsu/IEUAdrM[38]} {wallypipelinedsoc/hart/lsu/IEUAdrM[39]} {wallypipelinedsoc/hart/lsu/IEUAdrM[40]} {wallypipelinedsoc/hart/lsu/IEUAdrM[41]} {wallypipelinedsoc/hart/lsu/IEUAdrM[42]} {wallypipelinedsoc/hart/lsu/IEUAdrM[43]} {wallypipelinedsoc/hart/lsu/IEUAdrM[44]} {wallypipelinedsoc/hart/lsu/IEUAdrM[45]} {wallypipelinedsoc/hart/lsu/IEUAdrM[46]} {wallypipelinedsoc/hart/lsu/IEUAdrM[47]} {wallypipelinedsoc/hart/lsu/IEUAdrM[48]} {wallypipelinedsoc/hart/lsu/IEUAdrM[49]} {wallypipelinedsoc/hart/lsu/IEUAdrM[50]} {wallypipelinedsoc/hart/lsu/IEUAdrM[51]} {wallypipelinedsoc/hart/lsu/IEUAdrM[52]} {wallypipelinedsoc/hart/lsu/IEUAdrM[53]} {wallypipelinedsoc/hart/lsu/IEUAdrM[54]} {wallypipelinedsoc/hart/lsu/IEUAdrM[55]} ]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 56 [get_debug_ports u_ila_0/probe122]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe122]
|
||||
connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/hart/ifu/PCPFmmu[0]} {wallypipelinedsoc/hart/ifu/PCPFmmu[1]} {wallypipelinedsoc/hart/ifu/PCPFmmu[2]} {wallypipelinedsoc/hart/ifu/PCPFmmu[3]} {wallypipelinedsoc/hart/ifu/PCPFmmu[4]} {wallypipelinedsoc/hart/ifu/PCPFmmu[5]} {wallypipelinedsoc/hart/ifu/PCPFmmu[6]} {wallypipelinedsoc/hart/ifu/PCPFmmu[7]} {wallypipelinedsoc/hart/ifu/PCPFmmu[8]} {wallypipelinedsoc/hart/ifu/PCPFmmu[9]} {wallypipelinedsoc/hart/ifu/PCPFmmu[10]} {wallypipelinedsoc/hart/ifu/PCPFmmu[11]} {wallypipelinedsoc/hart/ifu/PCPFmmu[12]} {wallypipelinedsoc/hart/ifu/PCPFmmu[13]} {wallypipelinedsoc/hart/ifu/PCPFmmu[14]} {wallypipelinedsoc/hart/ifu/PCPFmmu[15]} {wallypipelinedsoc/hart/ifu/PCPFmmu[16]} {wallypipelinedsoc/hart/ifu/PCPFmmu[17]} {wallypipelinedsoc/hart/ifu/PCPFmmu[18]} {wallypipelinedsoc/hart/ifu/PCPFmmu[19]} {wallypipelinedsoc/hart/ifu/PCPFmmu[20]} {wallypipelinedsoc/hart/ifu/PCPFmmu[21]} {wallypipelinedsoc/hart/ifu/PCPFmmu[22]} {wallypipelinedsoc/hart/ifu/PCPFmmu[23]} {wallypipelinedsoc/hart/ifu/PCPFmmu[24]} {wallypipelinedsoc/hart/ifu/PCPFmmu[25]} {wallypipelinedsoc/hart/ifu/PCPFmmu[26]} {wallypipelinedsoc/hart/ifu/PCPFmmu[27]} {wallypipelinedsoc/hart/ifu/PCPFmmu[28]} {wallypipelinedsoc/hart/ifu/PCPFmmu[29]} {wallypipelinedsoc/hart/ifu/PCPFmmu[30]} {wallypipelinedsoc/hart/ifu/PCPFmmu[31]} {wallypipelinedsoc/hart/ifu/PCPFmmu[32]} {wallypipelinedsoc/hart/ifu/PCPFmmu[33]} {wallypipelinedsoc/hart/ifu/PCPFmmu[34]} {wallypipelinedsoc/hart/ifu/PCPFmmu[35]} {wallypipelinedsoc/hart/ifu/PCPFmmu[36]} {wallypipelinedsoc/hart/ifu/PCPFmmu[37]} {wallypipelinedsoc/hart/ifu/PCPFmmu[38]} {wallypipelinedsoc/hart/ifu/PCPFmmu[39]} {wallypipelinedsoc/hart/ifu/PCPFmmu[40]} {wallypipelinedsoc/hart/ifu/PCPFmmu[41]} {wallypipelinedsoc/hart/ifu/PCPFmmu[42]} {wallypipelinedsoc/hart/ifu/PCPFmmu[43]} {wallypipelinedsoc/hart/ifu/PCPFmmu[44]} {wallypipelinedsoc/hart/ifu/PCPFmmu[45]} {wallypipelinedsoc/hart/ifu/PCPFmmu[46]} {wallypipelinedsoc/hart/ifu/PCPFmmu[47]} {wallypipelinedsoc/hart/ifu/PCPFmmu[48]} {wallypipelinedsoc/hart/ifu/PCPFmmu[49]} {wallypipelinedsoc/hart/ifu/PCPFmmu[50]} {wallypipelinedsoc/hart/ifu/PCPFmmu[51]} {wallypipelinedsoc/hart/ifu/PCPFmmu[52]} {wallypipelinedsoc/hart/ifu/PCPFmmu[53]} {wallypipelinedsoc/hart/ifu/PCPFmmu[54]} {wallypipelinedsoc/hart/ifu/PCPFmmu[55]} ]]
|
||||
connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/hart/ifu/PCPF[0]} {wallypipelinedsoc/hart/ifu/PCPF[1]} {wallypipelinedsoc/hart/ifu/PCPF[2]} {wallypipelinedsoc/hart/ifu/PCPF[3]} {wallypipelinedsoc/hart/ifu/PCPF[4]} {wallypipelinedsoc/hart/ifu/PCPF[5]} {wallypipelinedsoc/hart/ifu/PCPF[6]} {wallypipelinedsoc/hart/ifu/PCPF[7]} {wallypipelinedsoc/hart/ifu/PCPF[8]} {wallypipelinedsoc/hart/ifu/PCPF[9]} {wallypipelinedsoc/hart/ifu/PCPF[10]} {wallypipelinedsoc/hart/ifu/PCPF[11]} {wallypipelinedsoc/hart/ifu/PCPF[12]} {wallypipelinedsoc/hart/ifu/PCPF[13]} {wallypipelinedsoc/hart/ifu/PCPF[14]} {wallypipelinedsoc/hart/ifu/PCPF[15]} {wallypipelinedsoc/hart/ifu/PCPF[16]} {wallypipelinedsoc/hart/ifu/PCPF[17]} {wallypipelinedsoc/hart/ifu/PCPF[18]} {wallypipelinedsoc/hart/ifu/PCPF[19]} {wallypipelinedsoc/hart/ifu/PCPF[20]} {wallypipelinedsoc/hart/ifu/PCPF[21]} {wallypipelinedsoc/hart/ifu/PCPF[22]} {wallypipelinedsoc/hart/ifu/PCPF[23]} {wallypipelinedsoc/hart/ifu/PCPF[24]} {wallypipelinedsoc/hart/ifu/PCPF[25]} {wallypipelinedsoc/hart/ifu/PCPF[26]} {wallypipelinedsoc/hart/ifu/PCPF[27]} {wallypipelinedsoc/hart/ifu/PCPF[28]} {wallypipelinedsoc/hart/ifu/PCPF[29]} {wallypipelinedsoc/hart/ifu/PCPF[30]} {wallypipelinedsoc/hart/ifu/PCPF[31]} {wallypipelinedsoc/hart/ifu/PCPF[32]} {wallypipelinedsoc/hart/ifu/PCPF[33]} {wallypipelinedsoc/hart/ifu/PCPF[34]} {wallypipelinedsoc/hart/ifu/PCPF[35]} {wallypipelinedsoc/hart/ifu/PCPF[36]} {wallypipelinedsoc/hart/ifu/PCPF[37]} {wallypipelinedsoc/hart/ifu/PCPF[38]} {wallypipelinedsoc/hart/ifu/PCPF[39]} {wallypipelinedsoc/hart/ifu/PCPF[40]} {wallypipelinedsoc/hart/ifu/PCPF[41]} {wallypipelinedsoc/hart/ifu/PCPF[42]} {wallypipelinedsoc/hart/ifu/PCPF[43]} {wallypipelinedsoc/hart/ifu/PCPF[44]} {wallypipelinedsoc/hart/ifu/PCPF[45]} {wallypipelinedsoc/hart/ifu/PCPF[46]} {wallypipelinedsoc/hart/ifu/PCPF[47]} {wallypipelinedsoc/hart/ifu/PCPF[48]} {wallypipelinedsoc/hart/ifu/PCPF[49]} {wallypipelinedsoc/hart/ifu/PCPF[50]} {wallypipelinedsoc/hart/ifu/PCPF[51]} {wallypipelinedsoc/hart/ifu/PCPF[52]} {wallypipelinedsoc/hart/ifu/PCPF[53]} {wallypipelinedsoc/hart/ifu/PCPF[54]} {wallypipelinedsoc/hart/ifu/PCPF[55]} ]]
|
||||
|
||||
|
||||
|
|
|
|||
141
pipelined/src/cache/cache.sv
vendored
141
pipelined/src/cache/cache.sv
vendored
|
|
@ -26,43 +26,40 @@
|
|||
`include "wally-config.vh"
|
||||
|
||||
module cache #(parameter integer LINELEN,
|
||||
parameter integer NUMLINES,
|
||||
parameter integer NUMWAYS,
|
||||
parameter integer NUMLINES,
|
||||
parameter integer NUMWAYS,
|
||||
parameter integer DCACHE = 1)
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic CPUBusy,
|
||||
|
||||
input logic reset,
|
||||
// cpu side
|
||||
input logic [1:0] RW,
|
||||
input logic [1:0] Atomic,
|
||||
input logic FlushCache,
|
||||
input logic [11:0] LsuAdrE, // virtual address, but we only use the lower 12 bits.
|
||||
input logic [`PA_BITS-1:0] LsuPAdrM, // physical address
|
||||
input logic [11:0] PreLsuPAdrM, // physical or virtual address
|
||||
input logic [`XLEN-1:0] FinalWriteData,
|
||||
output logic [`XLEN-1:0] ReadDataWord,
|
||||
output logic CacheCommitted,
|
||||
input logic CPUBusy,
|
||||
input logic [1:0] RW,
|
||||
input logic [1:0] Atomic,
|
||||
input logic FlushCache,
|
||||
input logic InvalidateCacheM,
|
||||
input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits.
|
||||
input logic [`PA_BITS-1:0] PAdr, // physical address
|
||||
input logic [11:0] NoTranAdr, // physical or virtual address
|
||||
input logic [`XLEN-1:0] FinalWriteData,
|
||||
output logic [`XLEN-1:0] ReadDataWord,
|
||||
output logic CacheCommitted,
|
||||
output logic CacheStall,
|
||||
|
||||
// to performance counters to cpu
|
||||
output logic CacheMiss,
|
||||
output logic CacheAccess,
|
||||
|
||||
// lsu control
|
||||
input logic IgnoreRequest,
|
||||
|
||||
// Bus fsm interface
|
||||
input logic IgnoreRequest,
|
||||
output logic CacheFetchLine,
|
||||
output logic CacheWriteLine,
|
||||
output logic CacheFetchLine,
|
||||
output logic CacheWriteLine,
|
||||
input logic CacheBusAck,
|
||||
|
||||
input logic CacheBusAck,
|
||||
output logic [`PA_BITS-1:0] CacheBusAdr,
|
||||
|
||||
|
||||
input logic [LINELEN-1:0] CacheMemWriteData,
|
||||
output logic [`XLEN-1:0] ReadDataLineSets [(LINELEN/`XLEN)-1:0],
|
||||
|
||||
output logic CacheStall,
|
||||
|
||||
// to performance counters
|
||||
output logic CacheMiss,
|
||||
output logic CacheAccess,
|
||||
input logic InvalidateCacheM
|
||||
);
|
||||
output logic [`XLEN-1:0] ReadDataLineSets [(LINELEN/`XLEN)-1:0]);
|
||||
|
||||
|
||||
localparam integer LINEBYTELEN = LINELEN/8;
|
||||
|
|
@ -73,7 +70,7 @@ module cache #(parameter integer LINELEN,
|
|||
localparam integer LOGWPL = $clog2(WORDSPERLINE);
|
||||
localparam integer LOGXLENBYTES = $clog2(`XLEN/8);
|
||||
|
||||
localparam integer FlushAdrThreshold = NUMLINES;
|
||||
localparam integer FlushAdrThreshold = NUMLINES - 1;
|
||||
|
||||
logic [1:0] SelAdr;
|
||||
logic [INDEXLEN-1:0] RAdr;
|
||||
|
|
@ -83,12 +80,12 @@ module cache #(parameter integer LINELEN,
|
|||
logic [LINELEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0];
|
||||
logic [NUMWAYS-1:0] WayHit;
|
||||
logic CacheHit;
|
||||
logic [LINELEN-1:0] ReadDataLineM;
|
||||
logic [LINELEN-1:0] ReadDataLine;
|
||||
logic [WORDSPERLINE-1:0] SRAMWordEnable;
|
||||
|
||||
logic SRAMWordWriteEnableM;
|
||||
logic SRAMLineWriteEnableM;
|
||||
logic [NUMWAYS-1:0] SRAMLineWayWriteEnableM;
|
||||
logic SRAMWordWriteEnable;
|
||||
logic SRAMLineWriteEnable;
|
||||
logic [NUMWAYS-1:0] SRAMLineWayWriteEnable;
|
||||
logic [NUMWAYS-1:0] SRAMWayWriteEnable;
|
||||
|
||||
|
||||
|
|
@ -96,19 +93,17 @@ module cache #(parameter integer LINELEN,
|
|||
logic [NUMWAYS-1:0] VictimDirtyWay;
|
||||
logic VictimDirty;
|
||||
|
||||
logic [2**LOGWPL-1:0] MemPAdrDecodedW;
|
||||
logic [2**LOGWPL-1:0] MemPAdrDecoded;
|
||||
|
||||
logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0];
|
||||
logic [TAGLEN-1:0] VictimTag;
|
||||
|
||||
logic [INDEXLEN-1:0] FlushAdr;
|
||||
logic [INDEXLEN-1:0] FlushAdrP1;
|
||||
logic [INDEXLEN-1:0] FlushAdrQ;
|
||||
logic [INDEXLEN-1:0] FlushAdrMux;
|
||||
logic SelLastFlushAdr;
|
||||
logic FlushAdrCntEn;
|
||||
logic FlushAdrCntRst;
|
||||
logic FlushAdrFlag;
|
||||
logic FlushWayFlag;
|
||||
|
||||
logic [NUMWAYS-1:0] FlushWay;
|
||||
logic [NUMWAYS-1:0] NextFlushWay;
|
||||
|
|
@ -124,24 +119,22 @@ module cache #(parameter integer LINELEN,
|
|||
// Read Path CPU (IEU) side
|
||||
|
||||
mux3 #(INDEXLEN)
|
||||
AdrSelMux(.d0(LsuAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d1(PreLsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d2(FlushAdrMux),
|
||||
AdrSelMux(.d0(NextAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d1(NoTranAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d2(FlushAdr),
|
||||
.s(SelAdr),
|
||||
.y(RAdr));
|
||||
|
||||
mux2 #(INDEXLEN)
|
||||
FlushAdrSelMux(.d0(FlushAdr), .d1(FlushAdrQ), .s(SelLastFlushAdr),
|
||||
.y(FlushAdrMux));
|
||||
|
||||
|
||||
|
||||
cacheway #(.NUMLINES(NUMLINES), .LINELEN(LINELEN), .TAGLEN(TAGLEN),
|
||||
.OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
|
||||
MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
|
||||
.PAdr(LsuPAdrM),
|
||||
.PAdr(PAdr),
|
||||
.WriteEnable(SRAMWayWriteEnable),
|
||||
.VDWriteEnable(VDWriteEnableWay),
|
||||
.WriteWordEnable(SRAMWordEnable),
|
||||
.TagWriteEnable(SRAMLineWayWriteEnableM),
|
||||
.TagWriteEnable(SRAMLineWayWriteEnable),
|
||||
.WriteData(SRAMWriteData),
|
||||
.SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict,
|
||||
.VictimWay, .FlushWay, .SelFlush,
|
||||
|
|
@ -154,7 +147,7 @@ module cache #(parameter integer LINELEN,
|
|||
cachereplacementpolicy(.clk, .reset,
|
||||
.WayHit,
|
||||
.VictimWay,
|
||||
.LsuPAdrM(LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.PAdr(PAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.RAdr,
|
||||
.LRUWriteEn);
|
||||
end else begin:vict
|
||||
|
|
@ -168,7 +161,7 @@ module cache #(parameter integer LINELEN,
|
|||
// ReadDataLineWayMaskedM is a 2d array of cache line len by number of ways.
|
||||
// Need to OR together each way in a bitwise manner.
|
||||
// Final part of the AO Mux. First is the AND in the cacheway.
|
||||
or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadDataLineM));
|
||||
or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadDataLine));
|
||||
or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag));
|
||||
|
||||
|
||||
|
|
@ -178,17 +171,17 @@ module cache #(parameter integer LINELEN,
|
|||
genvar index;
|
||||
if(DCACHE == 1) begin: readdata
|
||||
for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
|
||||
assign ReadDataLineSets[index] = ReadDataLineM[((index+1)*`XLEN)-1: (index*`XLEN)];
|
||||
assign ReadDataLineSets[index] = ReadDataLine[((index+1)*`XLEN)-1: (index*`XLEN)];
|
||||
end
|
||||
// variable input mux
|
||||
assign ReadDataWord = ReadDataLineSets[LsuPAdrM[LOGWPL + LOGXLENBYTES - 1 : LOGXLENBYTES]];
|
||||
assign ReadDataWord = ReadDataLineSets[PAdr[LOGWPL + LOGXLENBYTES - 1 : LOGXLENBYTES]];
|
||||
end else begin: readdata
|
||||
logic [31:0] ReadLineSetsF [LINELEN/16-1:0];
|
||||
logic [31:0] FinalInstrRawF;
|
||||
for(index = 0; index < LINELEN / 16 - 1; index++)
|
||||
assign ReadLineSetsF[index] = ReadDataLineM[((index+1)*16)+16-1 : (index*16)];
|
||||
assign ReadLineSetsF[LINELEN/16-1] = {16'b0, ReadDataLineM[LINELEN-1:LINELEN-16]};
|
||||
assign FinalInstrRawF = ReadLineSetsF[LsuPAdrM[$clog2(LINELEN / 32) + 1 : 1]];
|
||||
assign ReadLineSetsF[index] = ReadDataLine[((index+1)*16)+16-1 : (index*16)];
|
||||
assign ReadLineSetsF[LINELEN/16-1] = {16'b0, ReadDataLine[LINELEN-1:LINELEN-16]};
|
||||
assign FinalInstrRawF = ReadLineSetsF[PAdr[$clog2(LINELEN / 32) + 1 : 1]];
|
||||
if (`XLEN == 64) assign ReadDataWord = {32'b0, FinalInstrRawF};
|
||||
else assign ReadDataWord = FinalInstrRawF;
|
||||
end
|
||||
|
|
@ -196,29 +189,29 @@ module cache #(parameter integer LINELEN,
|
|||
// Write Path CPU (IEU) side
|
||||
|
||||
onehotdecoder #(LOGWPL)
|
||||
adrdec(.bin(LsuPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
|
||||
.decoded(MemPAdrDecodedW));
|
||||
adrdec(.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
|
||||
.decoded(MemPAdrDecoded));
|
||||
|
||||
assign SRAMWordEnable = SRAMLineWriteEnableM ? '1 : MemPAdrDecodedW;
|
||||
assign SRAMWordEnable = SRAMLineWriteEnable ? '1 : MemPAdrDecoded;
|
||||
|
||||
assign SRAMLineWayWriteEnableM = SRAMLineWriteEnableM ? VictimWay : '0;
|
||||
assign SRAMLineWayWriteEnable = SRAMLineWriteEnable ? VictimWay : '0;
|
||||
|
||||
mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableM ? WayHit : '0),
|
||||
.d1(SRAMLineWayWriteEnableM),
|
||||
.s(SRAMLineWriteEnableM),
|
||||
mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnable ? WayHit : '0),
|
||||
.d1(SRAMLineWayWriteEnable),
|
||||
.s(SRAMLineWriteEnable),
|
||||
.y(SRAMWayWriteEnable));
|
||||
|
||||
|
||||
|
||||
mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}),
|
||||
.d1(CacheMemWriteData),
|
||||
.s(SRAMLineWriteEnableM),
|
||||
.s(SRAMLineWriteEnable),
|
||||
.y(SRAMWriteData));
|
||||
|
||||
|
||||
mux3 #(`PA_BITS) BaseAdrMux(.d0({LsuPAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
||||
.d1({VictimTag, LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
||||
.d2({VictimTag, FlushAdrQ, {{OFFSETLEN}{1'b0}}}),
|
||||
mux3 #(`PA_BITS) BaseAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
||||
.d1({VictimTag, PAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
||||
.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
|
||||
.s({SelFlush, SelEvict}),
|
||||
.y(CacheBusAdr));
|
||||
|
||||
|
|
@ -228,17 +221,11 @@ module cache #(parameter integer LINELEN,
|
|||
flopenr #(INDEXLEN)
|
||||
FlushAdrReg(.clk,
|
||||
.reset(reset | FlushAdrCntRst),
|
||||
.en(FlushAdrCntEn & FlushWay[NUMWAYS-2]),
|
||||
.en(FlushAdrCntEn),
|
||||
.d(FlushAdrP1),
|
||||
.q(FlushAdr));
|
||||
assign FlushAdrP1 = FlushAdr + 1'b1;
|
||||
|
||||
flopenr #(INDEXLEN)
|
||||
FlushAdrQReg(.clk,
|
||||
.reset(reset | FlushAdrCntRst),
|
||||
.en(FlushAdrCntEn),
|
||||
.d(FlushAdr),
|
||||
.q(FlushAdrQ));
|
||||
|
||||
flopenl #(NUMWAYS)
|
||||
FlushWayReg(.clk,
|
||||
|
|
@ -252,7 +239,9 @@ module cache #(parameter integer LINELEN,
|
|||
|
||||
assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
|
||||
|
||||
assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];
|
||||
//assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];
|
||||
assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0];
|
||||
assign FlushWayFlag = FlushWay[NUMWAYS-1];
|
||||
|
||||
// controller
|
||||
// *** fixme
|
||||
|
|
@ -265,10 +254,10 @@ module cache #(parameter integer LINELEN,
|
|||
.RW, .Atomic, .CPUBusy, .CacheableM, .IgnoreRequest,
|
||||
.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
|
||||
.CacheMiss, .CacheAccess, .SelAdr, .SetValid,
|
||||
.ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM,
|
||||
.SRAMLineWriteEnableM, .SelEvict, .SelFlush,
|
||||
.ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnable,
|
||||
.SRAMLineWriteEnable, .SelEvict, .SelFlush,
|
||||
.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
|
||||
.FlushWayCntRst, .FlushAdrFlag, .FlushCache, .SelLastFlushAdr,
|
||||
.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache,
|
||||
.VDWriteEnable, .LRUWriteEn);
|
||||
|
||||
|
||||
|
|
|
|||
82
pipelined/src/cache/cachefsm.sv
vendored
82
pipelined/src/cache/cachefsm.sv
vendored
|
|
@ -43,6 +43,7 @@ module cachefsm
|
|||
input logic CacheHit,
|
||||
input logic VictimDirty,
|
||||
input logic FlushAdrFlag,
|
||||
input logic FlushWayFlag,
|
||||
|
||||
// hazard outputs
|
||||
output logic CacheStall,
|
||||
|
|
@ -60,12 +61,11 @@ module cachefsm
|
|||
output logic ClearValid,
|
||||
output logic SetDirty,
|
||||
output logic ClearDirty,
|
||||
output logic SRAMWordWriteEnableM,
|
||||
output logic SRAMLineWriteEnableM,
|
||||
output logic SRAMWordWriteEnable,
|
||||
output logic SRAMLineWriteEnable,
|
||||
output logic SelEvict,
|
||||
output logic LRUWriteEn,
|
||||
output logic SelFlush,
|
||||
output logic SelLastFlushAdr,
|
||||
output logic FlushAdrCntEn,
|
||||
output logic FlushWayCntEn,
|
||||
output logic FlushAdrCntRst,
|
||||
|
|
@ -90,6 +90,8 @@ module cachefsm
|
|||
STATE_CPU_BUSY_FINISH_AMO,
|
||||
|
||||
STATE_FLUSH,
|
||||
STATE_FLUSH_CHECK,
|
||||
STATE_FLUSH_INCR,
|
||||
STATE_FLUSH_WRITE_BACK,
|
||||
STATE_FLUSH_CLEAR_DIRTY} statetype;
|
||||
|
||||
|
|
@ -113,8 +115,8 @@ module cachefsm
|
|||
ClearValid = 1'b0;
|
||||
SetDirty = 1'b0;
|
||||
ClearDirty = 1'b0;
|
||||
SRAMWordWriteEnableM = 1'b0;
|
||||
SRAMLineWriteEnableM = 1'b0;
|
||||
SRAMWordWriteEnable = 1'b0;
|
||||
SRAMLineWriteEnable = 1'b0;
|
||||
SelEvict = 1'b0;
|
||||
LRUWriteEn = 1'b0;
|
||||
SelFlush = 1'b0;
|
||||
|
|
@ -126,14 +128,13 @@ module cachefsm
|
|||
NextState = STATE_READY;
|
||||
CacheFetchLine = 1'b0;
|
||||
CacheWriteLine = 1'b0;
|
||||
SelLastFlushAdr = 1'b0;
|
||||
|
||||
case (CurrState)
|
||||
STATE_READY: begin
|
||||
|
||||
CacheStall = 1'b0;
|
||||
SelAdr = 2'b00;
|
||||
SRAMWordWriteEnableM = 1'b0;
|
||||
SRAMWordWriteEnable = 1'b0;
|
||||
SetDirty = 1'b0;
|
||||
LRUWriteEn = 1'b0;
|
||||
|
||||
|
|
@ -152,10 +153,9 @@ module cachefsm
|
|||
// Flush dcache to next level of memory
|
||||
else if(FlushCache) begin
|
||||
NextState = STATE_FLUSH;
|
||||
CacheStall = 1'b1;
|
||||
SelAdr = 2'b10;
|
||||
FlushAdrCntRst = 1'b1;
|
||||
FlushWayCntRst = 1'b1;
|
||||
CacheStall = 1'b1;
|
||||
end
|
||||
|
||||
// amo hit
|
||||
|
|
@ -168,7 +168,7 @@ module cachefsm
|
|||
SelAdr = 2'b01;
|
||||
end
|
||||
else begin
|
||||
SRAMWordWriteEnableM = 1'b1;
|
||||
SRAMWordWriteEnable = 1'b1;
|
||||
SetDirty = 1'b1;
|
||||
LRUWriteEn = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
|
|
@ -191,7 +191,7 @@ module cachefsm
|
|||
else if (RW[0] & CacheableM & CacheHit) begin
|
||||
SelAdr = 2'b01;
|
||||
CacheStall = 1'b0;
|
||||
SRAMWordWriteEnableM = 1'b1;
|
||||
SRAMWordWriteEnable = 1'b1;
|
||||
SetDirty = 1'b1;
|
||||
LRUWriteEn = 1'b1;
|
||||
|
||||
|
|
@ -235,7 +235,7 @@ module cachefsm
|
|||
end
|
||||
|
||||
STATE_MISS_WRITE_CACHE_LINE: begin
|
||||
SRAMLineWriteEnableM = 1'b1;
|
||||
SRAMLineWriteEnable = 1'b1;
|
||||
CacheStall = 1'b1;
|
||||
NextState = STATE_MISS_READ_WORD;
|
||||
SelAdr = 2'b01;
|
||||
|
|
@ -258,7 +258,7 @@ module cachefsm
|
|||
|
||||
STATE_MISS_READ_WORD_DELAY: begin
|
||||
//SelAdr = 2'b01;
|
||||
SRAMWordWriteEnableM = 1'b0;
|
||||
SRAMWordWriteEnable = 1'b0;
|
||||
SetDirty = 1'b0;
|
||||
LRUWriteEn = 1'b0;
|
||||
if(&RW & Atomic[1]) begin // amo write
|
||||
|
|
@ -267,7 +267,7 @@ module cachefsm
|
|||
NextState = STATE_CPU_BUSY_FINISH_AMO;
|
||||
end
|
||||
else begin
|
||||
SRAMWordWriteEnableM = 1'b1;
|
||||
SRAMWordWriteEnable = 1'b1;
|
||||
SetDirty = 1'b1;
|
||||
LRUWriteEn = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
|
|
@ -285,7 +285,7 @@ module cachefsm
|
|||
end
|
||||
|
||||
STATE_MISS_WRITE_WORD: begin
|
||||
SRAMWordWriteEnableM = 1'b1;
|
||||
SRAMWordWriteEnable = 1'b1;
|
||||
SetDirty = 1'b1;
|
||||
SelAdr = 2'b01;
|
||||
LRUWriteEn = 1'b1;
|
||||
|
|
@ -323,48 +323,64 @@ module cachefsm
|
|||
|
||||
STATE_CPU_BUSY_FINISH_AMO: begin
|
||||
SelAdr = 2'b01;
|
||||
SRAMWordWriteEnableM = 1'b0;
|
||||
SRAMWordWriteEnable = 1'b0;
|
||||
SetDirty = 1'b0;
|
||||
LRUWriteEn = 1'b0;
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY_FINISH_AMO;
|
||||
end
|
||||
else begin
|
||||
SRAMWordWriteEnableM = 1'b1;
|
||||
SRAMWordWriteEnable = 1'b1;
|
||||
SetDirty = 1'b1;
|
||||
LRUWriteEn = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_FLUSH: begin
|
||||
STATE_FLUSH: begin
|
||||
// intialize flush counters
|
||||
SelFlush = 1'b1;
|
||||
CacheStall = 1'b1;
|
||||
SelAdr = 2'b10;
|
||||
NextState = STATE_FLUSH_CHECK;
|
||||
end
|
||||
|
||||
STATE_FLUSH_CHECK: begin
|
||||
CacheStall = 1'b1;
|
||||
SelAdr = 2'b10;
|
||||
SelFlush = 1'b1;
|
||||
FlushAdrCntEn = 1'b1;
|
||||
FlushWayCntEn = 1'b1;
|
||||
SelLastFlushAdr = 1'b0;
|
||||
if(VictimDirty) begin
|
||||
NextState = STATE_FLUSH_WRITE_BACK;
|
||||
FlushAdrCntEn = 1'b0;
|
||||
FlushWayCntEn = 1'b0;
|
||||
CacheWriteLine = 1'b1;
|
||||
SelLastFlushAdr = 1'b1;
|
||||
end else if (FlushAdrFlag) begin
|
||||
end else if (FlushAdrFlag & FlushWayFlag) begin
|
||||
NextState = STATE_READY;
|
||||
CacheStall = 1'b0;
|
||||
FlushAdrCntEn = 1'b0;
|
||||
SelAdr = 2'b00;
|
||||
FlushWayCntEn = 1'b0;
|
||||
end else if(FlushWayFlag) begin
|
||||
NextState = STATE_FLUSH_INCR;
|
||||
FlushAdrCntEn = 1'b1;
|
||||
|
||||
FlushWayCntEn = 1'b1;
|
||||
end else begin
|
||||
NextState = STATE_FLUSH;
|
||||
FlushWayCntEn = 1'b1;
|
||||
NextState = STATE_FLUSH_CHECK;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_FLUSH_INCR: begin
|
||||
CacheStall = 1'b1;
|
||||
SelAdr = 2'b10;
|
||||
SelFlush = 1'b1;
|
||||
FlushWayCntRst = 1'b1;
|
||||
NextState = STATE_FLUSH_CHECK;
|
||||
end
|
||||
|
||||
STATE_FLUSH_WRITE_BACK: begin
|
||||
CacheStall = 1'b1;
|
||||
SelAdr = 2'b10;
|
||||
SelFlush = 1'b1;
|
||||
SelLastFlushAdr = 1'b1;
|
||||
if(CacheBusAck) begin
|
||||
NextState = STATE_FLUSH_CLEAR_DIRTY;
|
||||
end else begin
|
||||
|
|
@ -378,16 +394,18 @@ module cachefsm
|
|||
VDWriteEnable = 1'b1;
|
||||
SelFlush = 1'b1;
|
||||
SelAdr = 2'b10;
|
||||
FlushAdrCntEn = 1'b0;
|
||||
FlushWayCntEn = 1'b0;
|
||||
SelLastFlushAdr = 1'b0;
|
||||
if(FlushAdrFlag) begin
|
||||
if(FlushAdrFlag & FlushWayFlag) begin
|
||||
NextState = STATE_READY;
|
||||
CacheStall = 1'b0;
|
||||
SelAdr = 2'b00;
|
||||
end else begin
|
||||
NextState = STATE_FLUSH;
|
||||
end else if (FlushWayFlag) begin
|
||||
NextState = STATE_FLUSH_INCR;
|
||||
FlushAdrCntEn = 1'b1;
|
||||
|
||||
FlushWayCntEn = 1'b1;
|
||||
end else begin
|
||||
NextState = STATE_FLUSH_CHECK;
|
||||
FlushWayCntEn = 1'b1;
|
||||
end
|
||||
end
|
||||
|
|
|
|||
12
pipelined/src/cache/cachereplacementpolicy.sv
vendored
12
pipelined/src/cache/cachereplacementpolicy.sv
vendored
|
|
@ -29,7 +29,7 @@ module cachereplacementpolicy
|
|||
(input logic clk, reset,
|
||||
input logic [NUMWAYS-1:0] WayHit,
|
||||
output logic [NUMWAYS-1:0] VictimWay,
|
||||
input logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] LsuPAdrM,
|
||||
input logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] PAdr,
|
||||
input logic [INDEXLEN-1:0] RAdr,
|
||||
input logic LRUWriteEn
|
||||
);
|
||||
|
|
@ -44,7 +44,7 @@ module cachereplacementpolicy
|
|||
logic [NUMWAYS-2:0] NewReplacement;
|
||||
logic [NUMWAYS-2:0] NewReplacementD;
|
||||
|
||||
logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] LsuPAdrMD;
|
||||
logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] PAdrD;
|
||||
logic [INDEXLEN-1:0] RAdrD;
|
||||
logic LRUWriteEnD;
|
||||
|
||||
|
|
@ -52,18 +52,18 @@ module cachereplacementpolicy
|
|||
always_ff @(posedge clk) begin
|
||||
if (reset) begin
|
||||
RAdrD <= '0;
|
||||
LsuPAdrMD <= '0;
|
||||
PAdrD <= '0;
|
||||
LRUWriteEnD <= 0;
|
||||
NewReplacementD <= '0;
|
||||
for(int index = 0; index < NUMLINES; index++)
|
||||
ReplacementBits[index] <= '0;
|
||||
ReplacementBits[index] <= '0;
|
||||
end else begin
|
||||
RAdrD <= RAdr;
|
||||
LsuPAdrMD <= LsuPAdrM;
|
||||
PAdrD <= PAdr;
|
||||
LRUWriteEnD <= LRUWriteEn;
|
||||
NewReplacementD <= NewReplacement;
|
||||
if (LRUWriteEnD) begin
|
||||
ReplacementBits[LsuPAdrMD[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacementD;
|
||||
ReplacementBits[PAdrD[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacementD;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
|||
8
pipelined/src/cache/cacheway.sv
vendored
8
pipelined/src/cache/cacheway.sv
vendored
|
|
@ -34,7 +34,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
|||
input logic [`PA_BITS-1:0] PAdr,
|
||||
input logic WriteEnable,
|
||||
input logic VDWriteEnable,
|
||||
input logic [LINELEN/`XLEN-1:0] WriteWordEnable,
|
||||
input logic [LINELEN/`XLEN-1:0] WriteWordEnable,
|
||||
input logic TagWriteEnable,
|
||||
input logic [LINELEN-1:0] WriteData,
|
||||
input logic SetValid,
|
||||
|
|
@ -73,14 +73,14 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
|||
|
||||
genvar words;
|
||||
for(words = 0; words < LINELEN/`XLEN; words++) begin: word
|
||||
sram1rw #(.DEPTH(`XLEN), .WIDTH(NUMLINES))
|
||||
sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN))
|
||||
CacheDataMem(.clk(clk), .Addr(RAdr),
|
||||
.ReadData(ReadDataLineWay[(words+1)*`XLEN-1:words*`XLEN] ),
|
||||
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
|
||||
.WriteEnable(WriteEnable & WriteWordEnable[words]));
|
||||
end
|
||||
|
||||
sram1rw #(.DEPTH(TAGLEN), .WIDTH(NUMLINES))
|
||||
sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN))
|
||||
CacheTagMem(.clk(clk),
|
||||
.Addr(RAdr),
|
||||
.ReadData(ReadTag),
|
||||
|
|
@ -135,6 +135,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
|||
end else begin:dirty
|
||||
assign Dirty = 1'b0;
|
||||
end
|
||||
|
||||
|
||||
endmodule // DCacheMemWay
|
||||
|
||||
|
||||
|
|
|
|||
254
pipelined/src/cache/dcache.sv
vendored
254
pipelined/src/cache/dcache.sv
vendored
|
|
@ -1,254 +0,0 @@
|
|||
///////////////////////////////////////////
|
||||
// dcache (data cache)
|
||||
//
|
||||
// Written: ross1728@gmail.com July 07, 2021
|
||||
// Implements the L1 data cache
|
||||
//
|
||||
// Purpose: Storage for data and meta data.
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module dcache #(parameter integer LINELEN,
|
||||
parameter integer NUMLINES,
|
||||
parameter integer NUMWAYS)
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic CPUBusy,
|
||||
|
||||
// mmu
|
||||
input logic CacheableM,
|
||||
// cpu side
|
||||
input logic [1:0] LsuRWM,
|
||||
input logic [1:0] LsuAtomicM,
|
||||
input logic FlushDCacheM,
|
||||
input logic [11:0] LsuAdrE, // virtual address, but we only use the lower 12 bits.
|
||||
input logic [`PA_BITS-1:0] LsuPAdrM, // physical address
|
||||
input logic [11:0] PreLsuPAdrM, // physical or virtual address
|
||||
input logic [`XLEN-1:0] FinalWriteDataM,
|
||||
output logic [`XLEN-1:0] ReadDataWordM,
|
||||
output logic DCacheCommittedM,
|
||||
|
||||
// Bus fsm interface
|
||||
input logic IgnoreRequest,
|
||||
output logic DCacheFetchLine,
|
||||
output logic DCacheWriteLine,
|
||||
|
||||
input logic DCacheBusAck,
|
||||
output logic [`PA_BITS-1:0] DCacheBusAdr,
|
||||
|
||||
|
||||
input logic [LINELEN-1:0] DCacheMemWriteData,
|
||||
output logic [`XLEN-1:0] ReadDataLineSetsM [(LINELEN/`XLEN)-1:0],
|
||||
|
||||
output logic DCacheStall,
|
||||
|
||||
// to performance counters
|
||||
output logic DCacheMiss,
|
||||
output logic DCacheAccess
|
||||
);
|
||||
|
||||
|
||||
localparam integer LINEBYTELEN = LINELEN/8;
|
||||
localparam integer OFFSETLEN = $clog2(LINEBYTELEN);
|
||||
localparam integer INDEXLEN = $clog2(NUMLINES);
|
||||
localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN;
|
||||
localparam integer WORDSPERLINE = LINELEN/`XLEN;
|
||||
localparam integer LOGWPL = $clog2(WORDSPERLINE);
|
||||
localparam integer LOGXLENBYTES = $clog2(`XLEN/8);
|
||||
|
||||
localparam integer FlushAdrThreshold = NUMLINES;
|
||||
|
||||
logic [1:0] SelAdrM;
|
||||
logic [INDEXLEN-1:0] RAdr;
|
||||
logic [LINELEN-1:0] SRAMWriteData;
|
||||
logic SetValid, ClearValid;
|
||||
logic SetDirty, ClearDirty;
|
||||
logic [LINELEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0];
|
||||
logic [NUMWAYS-1:0] WayHit;
|
||||
logic CacheHit;
|
||||
logic [LINELEN-1:0] ReadDataLineM;
|
||||
logic [WORDSPERLINE-1:0] SRAMWordEnable;
|
||||
|
||||
logic SRAMWordWriteEnableM;
|
||||
logic SRAMLineWriteEnableM;
|
||||
logic [NUMWAYS-1:0] SRAMLineWayWriteEnableM;
|
||||
logic [NUMWAYS-1:0] SRAMWayWriteEnable;
|
||||
|
||||
|
||||
logic [NUMWAYS-1:0] VictimWay;
|
||||
logic [NUMWAYS-1:0] VictimDirtyWay;
|
||||
logic VictimDirty;
|
||||
|
||||
logic [2**LOGWPL-1:0] MemPAdrDecodedW;
|
||||
|
||||
logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0];
|
||||
logic [TAGLEN-1:0] VictimTag;
|
||||
|
||||
logic [INDEXLEN-1:0] FlushAdr;
|
||||
logic [INDEXLEN-1:0] FlushAdrP1;
|
||||
logic [INDEXLEN-1:0] FlushAdrQ;
|
||||
logic FlushAdrCntEn;
|
||||
logic FlushAdrCntRst;
|
||||
logic FlushAdrFlag;
|
||||
|
||||
logic [NUMWAYS-1:0] FlushWay;
|
||||
logic [NUMWAYS-1:0] NextFlushWay;
|
||||
logic FlushWayCntEn;
|
||||
logic FlushWayCntRst;
|
||||
|
||||
logic VDWriteEnable;
|
||||
logic SelEvict;
|
||||
logic LRUWriteEn;
|
||||
logic [NUMWAYS-1:0] VDWriteEnableWay;
|
||||
logic SelFlush;
|
||||
|
||||
// Read Path CPU (IEU) side
|
||||
|
||||
mux3 #(INDEXLEN)
|
||||
AdrSelMux(.d0(LsuAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d1(PreLsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d2(FlushAdr),
|
||||
.s(SelAdrM),
|
||||
.y(RAdr));
|
||||
|
||||
cacheway #(.NUMLINES(NUMLINES), .LINELEN(LINELEN), .TAGLEN(TAGLEN),
|
||||
.OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
|
||||
MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
|
||||
.PAdr(LsuPAdrM),
|
||||
.WriteEnable(SRAMWayWriteEnable),
|
||||
.VDWriteEnable(VDWriteEnableWay),
|
||||
.WriteWordEnable(SRAMWordEnable),
|
||||
.TagWriteEnable(SRAMLineWayWriteEnableM),
|
||||
.WriteData(SRAMWriteData),
|
||||
.SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict,
|
||||
.VictimWay, .FlushWay, .SelFlush,
|
||||
.ReadDataLineWayMasked,
|
||||
.WayHit, .VictimDirtyWay, .VictimTagWay,
|
||||
.InvalidateAll(1'b0));
|
||||
|
||||
if(NUMWAYS > 1) begin:vict
|
||||
cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
|
||||
cachereplacementpolicy(.clk, .reset,
|
||||
.WayHit,
|
||||
.VictimWay,
|
||||
.LsuPAdrM(LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.RAdr,
|
||||
.LRUWriteEn);
|
||||
end else begin:vict
|
||||
assign VictimWay = 1'b1; // one hot.
|
||||
end
|
||||
|
||||
assign CacheHit = | WayHit;
|
||||
assign VictimDirty = | VictimDirtyWay;
|
||||
|
||||
|
||||
// ReadDataLineWayMaskedM is a 2d array of cache line len by number of ways.
|
||||
// Need to OR together each way in a bitwise manner.
|
||||
// Final part of the AO Mux. First is the AND in the cacheway.
|
||||
or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadDataLineM));
|
||||
or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag));
|
||||
|
||||
|
||||
// Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can
|
||||
// easily build a variable input mux.
|
||||
// *** consider using a limited range shift to do this final muxing.
|
||||
genvar index;
|
||||
for (index = 0; index < WORDSPERLINE; index++)
|
||||
assign ReadDataLineSetsM[index] = ReadDataLineM[((index+1)*`XLEN)-1: (index*`XLEN)];
|
||||
|
||||
// variable input mux
|
||||
|
||||
assign ReadDataWordM = ReadDataLineSetsM[LsuPAdrM[LOGWPL + LOGXLENBYTES - 1 : LOGXLENBYTES]];
|
||||
|
||||
// Write Path CPU (IEU) side
|
||||
|
||||
onehotdecoder #(LOGWPL)
|
||||
adrdec(.bin(LsuPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
|
||||
.decoded(MemPAdrDecodedW));
|
||||
|
||||
assign SRAMWordEnable = SRAMLineWriteEnableM ? '1 : MemPAdrDecodedW;
|
||||
|
||||
assign SRAMLineWayWriteEnableM = SRAMLineWriteEnableM ? VictimWay : '0;
|
||||
|
||||
mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableM ? WayHit : '0),
|
||||
.d1(SRAMLineWayWriteEnableM),
|
||||
.s(SRAMLineWriteEnableM),
|
||||
.y(SRAMWayWriteEnable));
|
||||
|
||||
|
||||
|
||||
mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteDataM}}),
|
||||
.d1(DCacheMemWriteData),
|
||||
.s(SRAMLineWriteEnableM),
|
||||
.y(SRAMWriteData));
|
||||
|
||||
|
||||
mux3 #(`PA_BITS) BaseAdrMux(.d0({LsuPAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
||||
.d1({VictimTag, LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
||||
.d2({VictimTag, FlushAdrQ, {{OFFSETLEN}{1'b0}}}),
|
||||
.s({SelFlush, SelEvict}),
|
||||
.y(DCacheBusAdr));
|
||||
|
||||
|
||||
// flush address and way generation.
|
||||
// increment on 2nd to last way
|
||||
flopenr #(INDEXLEN)
|
||||
FlushAdrReg(.clk,
|
||||
.reset(reset | FlushAdrCntRst),
|
||||
.en(FlushAdrCntEn & FlushWay[NUMWAYS-2]),
|
||||
.d(FlushAdrP1),
|
||||
.q(FlushAdr));
|
||||
assign FlushAdrP1 = FlushAdr + 1'b1;
|
||||
|
||||
flopenr #(INDEXLEN)
|
||||
FlushAdrQReg(.clk,
|
||||
.reset(reset | FlushAdrCntRst),
|
||||
.en(FlushAdrCntEn),
|
||||
.d(FlushAdr),
|
||||
.q(FlushAdrQ));
|
||||
|
||||
flopenl #(NUMWAYS)
|
||||
FlushWayReg(.clk,
|
||||
.load(reset | FlushWayCntRst),
|
||||
.en(FlushWayCntEn),
|
||||
.val({{NUMWAYS-1{1'b0}}, 1'b1}),
|
||||
.d(NextFlushWay),
|
||||
.q(FlushWay));
|
||||
|
||||
assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}};
|
||||
|
||||
assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
|
||||
|
||||
assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];
|
||||
|
||||
// controller
|
||||
|
||||
dcachefsm dcachefsm(.clk, .reset, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck,
|
||||
.LsuRWM, .LsuAtomicM, .CPUBusy, .CacheableM, .IgnoreRequest,
|
||||
.CacheHit, .VictimDirty, .DCacheStall, .DCacheCommittedM,
|
||||
.DCacheMiss, .DCacheAccess, .SelAdrM, .SetValid,
|
||||
.ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM,
|
||||
.SRAMLineWriteEnableM, .SelEvict, .SelFlush,
|
||||
.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
|
||||
.FlushWayCntRst, .FlushAdrFlag, .FlushDCacheM,
|
||||
.VDWriteEnable, .LRUWriteEn);
|
||||
|
||||
|
||||
endmodule // dcache
|
||||
398
pipelined/src/cache/dcachefsm.sv
vendored
398
pipelined/src/cache/dcachefsm.sv
vendored
|
|
@ -1,398 +0,0 @@
|
|||
///////////////////////////////////////////
|
||||
// dcache (data cache) fsm
|
||||
//
|
||||
// Written: ross1728@gmail.com August 25, 2021
|
||||
// Implements the L1 data cache fsm
|
||||
//
|
||||
// Purpose: Controller for the dcache fsm
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module dcachefsm
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
// inputs from IEU
|
||||
input logic [1:0] LsuRWM,
|
||||
input logic [1:0] LsuAtomicM,
|
||||
input logic FlushDCacheM,
|
||||
// hazard inputs
|
||||
input logic CPUBusy,
|
||||
input logic CacheableM,
|
||||
// interlock fsm
|
||||
input logic IgnoreRequest,
|
||||
// Bus inputs
|
||||
input logic DCacheBusAck,
|
||||
// dcache internals
|
||||
input logic CacheHit,
|
||||
input logic VictimDirty,
|
||||
input logic FlushAdrFlag,
|
||||
|
||||
// hazard outputs
|
||||
output logic DCacheStall,
|
||||
// counter outputs
|
||||
output logic DCacheMiss,
|
||||
output logic DCacheAccess,
|
||||
// Bus outputs
|
||||
output logic DCacheCommittedM,
|
||||
output logic DCacheWriteLine,
|
||||
output logic DCacheFetchLine,
|
||||
|
||||
// dcache internals
|
||||
output logic [1:0] SelAdrM,
|
||||
output logic SetValid,
|
||||
output logic ClearValid,
|
||||
output logic SetDirty,
|
||||
output logic ClearDirty,
|
||||
output logic SRAMWordWriteEnableM,
|
||||
output logic SRAMLineWriteEnableM,
|
||||
output logic SelEvict,
|
||||
output logic LRUWriteEn,
|
||||
output logic SelFlush,
|
||||
output logic FlushAdrCntEn,
|
||||
output logic FlushWayCntEn,
|
||||
output logic FlushAdrCntRst,
|
||||
output logic FlushWayCntRst,
|
||||
output logic VDWriteEnable
|
||||
|
||||
);
|
||||
|
||||
logic AnyCPUReqM;
|
||||
|
||||
typedef enum {STATE_READY,
|
||||
|
||||
STATE_MISS_FETCH_WDV,
|
||||
STATE_MISS_FETCH_DONE,
|
||||
STATE_MISS_EVICT_DIRTY,
|
||||
STATE_MISS_WRITE_CACHE_LINE,
|
||||
STATE_MISS_READ_WORD,
|
||||
STATE_MISS_READ_WORD_DELAY,
|
||||
STATE_MISS_WRITE_WORD,
|
||||
|
||||
STATE_CPU_BUSY,
|
||||
STATE_CPU_BUSY_FINISH_AMO,
|
||||
|
||||
STATE_FLUSH,
|
||||
STATE_FLUSH_WRITE_BACK,
|
||||
STATE_FLUSH_CLEAR_DIRTY} statetype;
|
||||
|
||||
(* mark_debug = "true" *) statetype CurrState, NextState;
|
||||
|
||||
assign AnyCPUReqM = |LsuRWM | (|LsuAtomicM);
|
||||
|
||||
// outputs for the performance counters.
|
||||
assign DCacheAccess = AnyCPUReqM & CacheableM & CurrState == STATE_READY;
|
||||
assign DCacheMiss = DCacheAccess & CacheableM & ~CacheHit;
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) CurrState <= #1 STATE_READY;
|
||||
else CurrState <= #1 NextState;
|
||||
|
||||
// next state logic and some state ouputs.
|
||||
always_comb begin
|
||||
DCacheStall = 1'b0;
|
||||
SelAdrM = 2'b00;
|
||||
SetValid = 1'b0;
|
||||
ClearValid = 1'b0;
|
||||
SetDirty = 1'b0;
|
||||
ClearDirty = 1'b0;
|
||||
SRAMWordWriteEnableM = 1'b0;
|
||||
SRAMLineWriteEnableM = 1'b0;
|
||||
SelEvict = 1'b0;
|
||||
LRUWriteEn = 1'b0;
|
||||
SelFlush = 1'b0;
|
||||
FlushAdrCntEn = 1'b0;
|
||||
FlushWayCntEn = 1'b0;
|
||||
FlushAdrCntRst = 1'b0;
|
||||
FlushWayCntRst = 1'b0;
|
||||
VDWriteEnable = 1'b0;
|
||||
NextState = STATE_READY;
|
||||
DCacheFetchLine = 1'b0;
|
||||
DCacheWriteLine = 1'b0;
|
||||
|
||||
case (CurrState)
|
||||
STATE_READY: begin
|
||||
|
||||
DCacheStall = 1'b0;
|
||||
SelAdrM = 2'b00;
|
||||
SRAMWordWriteEnableM = 1'b0;
|
||||
SetDirty = 1'b0;
|
||||
LRUWriteEn = 1'b0;
|
||||
|
||||
// TLB Miss
|
||||
if(IgnoreRequest) begin
|
||||
// the LSU arbiter has not yet selected the PTW.
|
||||
// The CPU needs to be stalled until that happens.
|
||||
// If we set DCacheStall for 1 cycle before going to
|
||||
// PTW ready the CPU will stall.
|
||||
// The page table walker asserts it's control 1 cycle
|
||||
// after the TLBs miss.
|
||||
SelAdrM = 2'b01;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
|
||||
// Flush dcache to next level of memory
|
||||
else if(FlushDCacheM) begin
|
||||
NextState = STATE_FLUSH;
|
||||
DCacheStall = 1'b1;
|
||||
SelAdrM = 2'b10;
|
||||
FlushAdrCntRst = 1'b1;
|
||||
FlushWayCntRst = 1'b1;
|
||||
end
|
||||
|
||||
// amo hit
|
||||
else if(LsuAtomicM[1] & (&LsuRWM) & CacheableM & CacheHit) begin
|
||||
SelAdrM = 2'b01;
|
||||
DCacheStall = 1'b0;
|
||||
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY_FINISH_AMO;
|
||||
SelAdrM = 2'b01;
|
||||
end
|
||||
else begin
|
||||
SRAMWordWriteEnableM = 1'b1;
|
||||
SetDirty = 1'b1;
|
||||
LRUWriteEn = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
// read hit valid cached
|
||||
else if(LsuRWM[1] & CacheableM & CacheHit) begin
|
||||
DCacheStall = 1'b0;
|
||||
LRUWriteEn = 1'b1;
|
||||
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdrM = 2'b01;
|
||||
end
|
||||
else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
// write hit valid cached
|
||||
else if (LsuRWM[0] & CacheableM & CacheHit) begin
|
||||
SelAdrM = 2'b01;
|
||||
DCacheStall = 1'b0;
|
||||
SRAMWordWriteEnableM = 1'b1;
|
||||
SetDirty = 1'b1;
|
||||
LRUWriteEn = 1'b1;
|
||||
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdrM = 2'b01;
|
||||
end
|
||||
else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
// read or write miss valid cached
|
||||
else if((|LsuRWM) & CacheableM & ~CacheHit) begin
|
||||
NextState = STATE_MISS_FETCH_WDV;
|
||||
DCacheStall = 1'b1;
|
||||
DCacheFetchLine = 1'b1;
|
||||
end
|
||||
else NextState = STATE_READY;
|
||||
end
|
||||
|
||||
STATE_MISS_FETCH_WDV: begin
|
||||
DCacheStall = 1'b1;
|
||||
SelAdrM = 2'b01;
|
||||
|
||||
if (DCacheBusAck) begin
|
||||
NextState = STATE_MISS_FETCH_DONE;
|
||||
end else begin
|
||||
NextState = STATE_MISS_FETCH_WDV;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_MISS_FETCH_DONE: begin
|
||||
DCacheStall = 1'b1;
|
||||
SelAdrM = 2'b01;
|
||||
if(VictimDirty) begin
|
||||
NextState = STATE_MISS_EVICT_DIRTY;
|
||||
DCacheWriteLine = 1'b1;
|
||||
end else begin
|
||||
NextState = STATE_MISS_WRITE_CACHE_LINE;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_MISS_WRITE_CACHE_LINE: begin
|
||||
SRAMLineWriteEnableM = 1'b1;
|
||||
DCacheStall = 1'b1;
|
||||
NextState = STATE_MISS_READ_WORD;
|
||||
SelAdrM = 2'b01;
|
||||
SetValid = 1'b1;
|
||||
ClearDirty = 1'b1;
|
||||
//LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write
|
||||
end
|
||||
|
||||
STATE_MISS_READ_WORD: begin
|
||||
SelAdrM = 2'b01;
|
||||
DCacheStall = 1'b1;
|
||||
if (LsuRWM[0] & ~LsuAtomicM[1]) begin // handles stores and amo write.
|
||||
NextState = STATE_MISS_WRITE_WORD;
|
||||
end else begin
|
||||
NextState = STATE_MISS_READ_WORD_DELAY;
|
||||
// delay state is required as the read signal LsuRWM[1] is still high when we
|
||||
// return to the ready state because the cache is stalling the cpu.
|
||||
end
|
||||
end
|
||||
|
||||
STATE_MISS_READ_WORD_DELAY: begin
|
||||
//SelAdrM = 2'b01;
|
||||
SRAMWordWriteEnableM = 1'b0;
|
||||
SetDirty = 1'b0;
|
||||
LRUWriteEn = 1'b0;
|
||||
if(&LsuRWM & LsuAtomicM[1]) begin // amo write
|
||||
SelAdrM = 2'b01;
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY_FINISH_AMO;
|
||||
end
|
||||
else begin
|
||||
SRAMWordWriteEnableM = 1'b1;
|
||||
SetDirty = 1'b1;
|
||||
LRUWriteEn = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end else begin
|
||||
LRUWriteEn = 1'b1;
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdrM = 2'b01;
|
||||
end
|
||||
else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
STATE_MISS_WRITE_WORD: begin
|
||||
SRAMWordWriteEnableM = 1'b1;
|
||||
SetDirty = 1'b1;
|
||||
SelAdrM = 2'b01;
|
||||
LRUWriteEn = 1'b1;
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdrM = 2'b01;
|
||||
end
|
||||
else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_MISS_EVICT_DIRTY: begin
|
||||
DCacheStall = 1'b1;
|
||||
SelAdrM = 2'b01;
|
||||
SelEvict = 1'b1;
|
||||
if(DCacheBusAck) begin
|
||||
NextState = STATE_MISS_WRITE_CACHE_LINE;
|
||||
end else begin
|
||||
NextState = STATE_MISS_EVICT_DIRTY;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
STATE_CPU_BUSY: begin
|
||||
SelAdrM = 2'b00;
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdrM = 2'b01;
|
||||
end
|
||||
else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_CPU_BUSY_FINISH_AMO: begin
|
||||
SelAdrM = 2'b01;
|
||||
SRAMWordWriteEnableM = 1'b0;
|
||||
SetDirty = 1'b0;
|
||||
LRUWriteEn = 1'b0;
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY_FINISH_AMO;
|
||||
end
|
||||
else begin
|
||||
SRAMWordWriteEnableM = 1'b1;
|
||||
SetDirty = 1'b1;
|
||||
LRUWriteEn = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_FLUSH: begin
|
||||
DCacheStall = 1'b1;
|
||||
SelAdrM = 2'b10;
|
||||
SelFlush = 1'b1;
|
||||
FlushAdrCntEn = 1'b1;
|
||||
FlushWayCntEn = 1'b1;
|
||||
if(VictimDirty) begin
|
||||
NextState = STATE_FLUSH_WRITE_BACK;
|
||||
FlushAdrCntEn = 1'b0;
|
||||
FlushWayCntEn = 1'b0;
|
||||
DCacheWriteLine = 1'b1;
|
||||
end else if (FlushAdrFlag) begin
|
||||
NextState = STATE_READY;
|
||||
DCacheStall = 1'b0;
|
||||
FlushAdrCntEn = 1'b0;
|
||||
FlushWayCntEn = 1'b0;
|
||||
end else begin
|
||||
NextState = STATE_FLUSH;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_FLUSH_WRITE_BACK: begin
|
||||
DCacheStall = 1'b1;
|
||||
SelAdrM = 2'b10;
|
||||
SelFlush = 1'b1;
|
||||
if(DCacheBusAck) begin
|
||||
NextState = STATE_FLUSH_CLEAR_DIRTY;
|
||||
end else begin
|
||||
NextState = STATE_FLUSH_WRITE_BACK;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_FLUSH_CLEAR_DIRTY: begin
|
||||
DCacheStall = 1'b1;
|
||||
ClearDirty = 1'b1;
|
||||
VDWriteEnable = 1'b1;
|
||||
SelFlush = 1'b1;
|
||||
SelAdrM = 2'b10;
|
||||
FlushAdrCntEn = 1'b0;
|
||||
FlushWayCntEn = 1'b0;
|
||||
if(FlushAdrFlag) begin
|
||||
NextState = STATE_READY;
|
||||
DCacheStall = 1'b0;
|
||||
SelAdrM = 2'b00;
|
||||
end else begin
|
||||
NextState = STATE_FLUSH;
|
||||
FlushAdrCntEn = 1'b1;
|
||||
FlushWayCntEn = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
default: begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
assign DCacheCommittedM = CurrState != STATE_READY;
|
||||
|
||||
endmodule // dcachefsm
|
||||
|
||||
165
pipelined/src/cache/icache.sv
vendored
165
pipelined/src/cache/icache.sv
vendored
|
|
@ -1,165 +0,0 @@
|
|||
///////////////////////////////////////////
|
||||
// icache.sv
|
||||
//
|
||||
// Written: jaallen@g.hmc.edu 2021-03-02
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Cache instructions for the ifu so it can access memory less often, saving cycles
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module icache #(parameter integer LINELEN,
|
||||
parameter integer NUMLINES,
|
||||
parameter integer NUMWAYS)
|
||||
(
|
||||
// Basic pipeline stuff
|
||||
input logic clk, reset,
|
||||
input logic CPUBusy,
|
||||
|
||||
// mmu
|
||||
input logic [1:0] IfuRWF,
|
||||
|
||||
// cpu side
|
||||
input logic InvalidateICacheM,
|
||||
input logic [11:0] PCNextF,
|
||||
input logic [`PA_BITS-1:0] PCPF,
|
||||
input logic [`XLEN-1:0] PCF,
|
||||
|
||||
// bus fsm interface
|
||||
input logic IgnoreRequest,
|
||||
input logic [LINELEN-1:0] ICacheMemWriteData,
|
||||
output logic ICacheFetchLine,
|
||||
|
||||
(* mark_debug = "true" *) input logic ICacheBusAck,
|
||||
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] ICacheBusAdr,
|
||||
// High if the icache is requesting a stall
|
||||
output logic ICacheStallF,
|
||||
|
||||
// The raw (not decompressed) instruction that was requested
|
||||
// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
|
||||
(* mark_debug = "true" *) output logic [31:0] FinalInstrRawF
|
||||
);
|
||||
|
||||
// Configuration parameters
|
||||
localparam integer LINEBYTELEN = LINELEN/8;
|
||||
|
||||
localparam integer OFFSETLEN = $clog2(LINEBYTELEN);
|
||||
localparam integer INDEXLEN = $clog2(NUMLINES);
|
||||
localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN;
|
||||
|
||||
// *** not used?
|
||||
localparam WORDSPERLINE = LINELEN/`XLEN;
|
||||
localparam LOGWPL = $clog2(WORDSPERLINE);
|
||||
|
||||
|
||||
|
||||
|
||||
// Input signals to cache memory
|
||||
logic ICacheMemWriteEnable;
|
||||
// Output signals from cache memory
|
||||
logic [LINELEN-1:0] ReadLineF;
|
||||
logic SelAdr;
|
||||
logic [INDEXLEN-1:0] RAdr;
|
||||
logic [NUMWAYS-1:0] VictimWay;
|
||||
logic LRUWriteEn;
|
||||
logic [NUMWAYS-1:0] WayHit;
|
||||
logic hit;
|
||||
|
||||
|
||||
logic [LINELEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0];
|
||||
|
||||
logic [31:0] ReadLineSetsF [LINELEN/16-1:0];
|
||||
|
||||
logic [NUMWAYS-1:0] SRAMWayWriteEnable;
|
||||
|
||||
|
||||
mux2 #(INDEXLEN)
|
||||
AdrSelMux(.d0(PCNextF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d1(PCF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.s(SelAdr),
|
||||
.y(RAdr));
|
||||
|
||||
|
||||
cacheway #(.NUMLINES(NUMLINES), .LINELEN(LINELEN), .TAGLEN(TAGLEN),
|
||||
.OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN), .DIRTY_BITS(0))
|
||||
MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
|
||||
.PAdr(PCPF),
|
||||
.WriteEnable(SRAMWayWriteEnable),
|
||||
.VDWriteEnable(1'b0),
|
||||
.WriteWordEnable({{(LINELEN/`XLEN){1'b1}}}),
|
||||
.TagWriteEnable(SRAMWayWriteEnable),
|
||||
.WriteData(ICacheMemWriteData),
|
||||
.SetValid(ICacheMemWriteEnable),
|
||||
.ClearValid(1'b0), .SetDirty(1'b0), .ClearDirty(1'b0), .SelEvict(1'b0),
|
||||
.VictimWay,
|
||||
.FlushWay(1'b0), .SelFlush(1'b0),
|
||||
.ReadDataLineWayMasked, .WayHit,
|
||||
.VictimDirtyWay(), .VictimTagWay(),
|
||||
.InvalidateAll(InvalidateICacheM));
|
||||
|
||||
if(NUMWAYS > 1) begin:vict
|
||||
cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
|
||||
cachereplacementpolicy(.clk, .reset,
|
||||
.WayHit,
|
||||
.VictimWay,
|
||||
.LsuPAdrM(PCPF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.RAdr,
|
||||
.LRUWriteEn);
|
||||
end else begin:vict
|
||||
assign VictimWay = 1'b1; // one hot.
|
||||
end
|
||||
|
||||
assign hit = | WayHit;
|
||||
|
||||
// ReadDataLineWayMasked is a 2d array of cache line len by number of ways.
|
||||
// Need to OR together each way in a bitwise manner.
|
||||
// Final part of the AO Mux. First is the AND in the cacheway.
|
||||
or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadLineF));
|
||||
|
||||
genvar index;
|
||||
for(index = 0; index < LINELEN / 16 - 1; index++)
|
||||
assign ReadLineSetsF[index] = ReadLineF[((index+1)*16)+16-1 : (index*16)];
|
||||
assign ReadLineSetsF[LINELEN/16-1] = {16'b0, ReadLineF[LINELEN-1:LINELEN-16]};
|
||||
|
||||
assign FinalInstrRawF = ReadLineSetsF[PCPF[$clog2(LINELEN / 32) + 1 : 1]];
|
||||
|
||||
assign ICacheBusAdr = {PCPF[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}};
|
||||
|
||||
|
||||
// truncate the offset from PCPF for memory address generation
|
||||
|
||||
assign SRAMWayWriteEnable = ICacheMemWriteEnable ? VictimWay : '0;
|
||||
|
||||
|
||||
icachefsm icachefsm(.clk,
|
||||
.reset,
|
||||
.CPUBusy,
|
||||
.ICacheMemWriteEnable,
|
||||
.ICacheStallF,
|
||||
.IgnoreRequest,
|
||||
.ICacheBusAck,
|
||||
.ICacheFetchLine,
|
||||
.IfuRWF,
|
||||
.hit,
|
||||
.SelAdr,
|
||||
.LRUWriteEn);
|
||||
|
||||
endmodule
|
||||
|
||||
164
pipelined/src/cache/icachefsm.sv
vendored
164
pipelined/src/cache/icachefsm.sv
vendored
|
|
@ -1,164 +0,0 @@
|
|||
///////////////////////////////////////////
|
||||
// icache.sv
|
||||
//
|
||||
// Written: ross1728@gmail.com June 04, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: I Cache controller
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module icachefsm
|
||||
(// Inputs from pipeline
|
||||
input logic clk, reset,
|
||||
|
||||
input logic CPUBusy,
|
||||
|
||||
input logic IgnoreRequest,
|
||||
input logic [1:0] IfuRWF,
|
||||
|
||||
// BUS interface
|
||||
input logic ICacheBusAck,
|
||||
|
||||
// icache internal inputs
|
||||
input logic hit,
|
||||
|
||||
// Load data into the cache
|
||||
output logic ICacheMemWriteEnable,
|
||||
|
||||
// Outputs to pipeline control stuff
|
||||
output logic ICacheStallF,
|
||||
|
||||
// Bus interface outputs
|
||||
output logic ICacheFetchLine,
|
||||
|
||||
// icache internal outputs
|
||||
output logic SelAdr,
|
||||
output logic LRUWriteEn
|
||||
);
|
||||
|
||||
// FSM states
|
||||
typedef enum {STATE_READY,
|
||||
|
||||
STATE_MISS_FETCH_WDV, // aligned miss, issue read to AHB and wait for data.
|
||||
STATE_MISS_FETCH_DONE, // write data into SRAM/LUT
|
||||
STATE_MISS_READ, // read line 1 from SRAM/LUT
|
||||
STATE_MISS_READ_DELAY, // read line 1 from SRAM/LUT
|
||||
|
||||
STATE_CPU_BUSY
|
||||
} statetype;
|
||||
|
||||
(* mark_debug = "true" *) statetype CurrState, NextState;
|
||||
logic PreCntEn;
|
||||
|
||||
// the FSM is always runing, do not stall.
|
||||
always_ff @(posedge clk)
|
||||
if (reset) CurrState <= #1 STATE_READY;
|
||||
else CurrState <= #1 NextState;
|
||||
|
||||
// Next state logic
|
||||
always_comb begin
|
||||
//IfuBusFetch = 1'b0;
|
||||
ICacheMemWriteEnable = 1'b0;
|
||||
SelAdr = 1'b0;
|
||||
ICacheStallF = 1'b1;
|
||||
LRUWriteEn = 1'b0;
|
||||
case (CurrState)
|
||||
STATE_READY: begin
|
||||
SelAdr = 1'b0;
|
||||
if(IgnoreRequest) begin
|
||||
SelAdr = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
ICacheStallF = 1'b0;
|
||||
end
|
||||
else if (IfuRWF[1] & hit) begin
|
||||
ICacheStallF = 1'b0;
|
||||
LRUWriteEn = 1'b1;
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdr = 1'b1;
|
||||
end else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end else if (IfuRWF[1] & ~hit) begin
|
||||
SelAdr = 1'b1; /// *********(
|
||||
NextState = STATE_MISS_FETCH_WDV;
|
||||
end else begin
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdr = 1'b1;
|
||||
ICacheStallF = 1'b0;
|
||||
end else begin
|
||||
ICacheStallF = 1'b0;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
end
|
||||
// branch 3 miss no spill
|
||||
STATE_MISS_FETCH_WDV: begin
|
||||
SelAdr = 1'b1;
|
||||
//IfuBusFetch = 1'b1;
|
||||
if (ICacheBusAck) begin
|
||||
NextState = STATE_MISS_FETCH_DONE;
|
||||
end else begin
|
||||
NextState = STATE_MISS_FETCH_WDV;
|
||||
end
|
||||
end
|
||||
STATE_MISS_FETCH_DONE: begin
|
||||
SelAdr = 1'b1;
|
||||
ICacheMemWriteEnable = 1'b1;
|
||||
NextState = STATE_MISS_READ;
|
||||
end
|
||||
STATE_MISS_READ: begin
|
||||
SelAdr = 1'b1;
|
||||
NextState = STATE_MISS_READ_DELAY;
|
||||
end
|
||||
STATE_MISS_READ_DELAY: begin
|
||||
ICacheStallF = 1'b0;
|
||||
LRUWriteEn = 1'b1;
|
||||
if(CPUBusy) begin
|
||||
SelAdr = 1'b1;
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdr = 1'b1;
|
||||
end else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
STATE_CPU_BUSY: begin
|
||||
ICacheStallF = 1'b0;
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdr = 1'b1;
|
||||
end
|
||||
else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
SelAdr = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
assign ICacheFetchLine = CurrState == STATE_MISS_FETCH_WDV;
|
||||
|
||||
|
||||
endmodule
|
||||
82
pipelined/src/cache/sram1rw.sv
vendored
82
pipelined/src/cache/sram1rw.sv
vendored
|
|
@ -1,73 +1,61 @@
|
|||
/* -----\/----- EXCLUDED -----\/-----
|
||||
// Depth is number of bits in one "word" of the memory, width is number of such words
|
||||
///////////////////////////////////////////
|
||||
// 1 port sram.
|
||||
//
|
||||
// Written: ross1728@gmail.com May 3, 2021
|
||||
// Basic sram with 1 read write port.
|
||||
// When clk rises Addr and WriteData are sampled.
|
||||
// Following the clk edge read data is output from the sampled Addr.
|
||||
// Write
|
||||
//
|
||||
// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
/-* verilator lint_off ASSIGNDLY *-/
|
||||
// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
|
||||
|
||||
module sram1rw #(parameter DEPTH=128, WIDTH=256) (
|
||||
input logic clk,
|
||||
// port 1 is read only
|
||||
input logic [$clog2(WIDTH)-1:0] Addr,
|
||||
output logic [DEPTH-1:0] ReadData,
|
||||
input logic [$clog2(DEPTH)-1:0] Addr,
|
||||
output logic [WIDTH-1:0] ReadData,
|
||||
|
||||
// port 2 is write only
|
||||
input logic [DEPTH-1:0] WriteData,
|
||||
input logic [WIDTH-1:0] WriteData,
|
||||
input logic WriteEnable
|
||||
);
|
||||
|
||||
logic [WIDTH-1:0][DEPTH-1:0] StoredData;
|
||||
logic [$clog2(WIDTH)-1:0] AddrD;
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
AddrD <= Addr;
|
||||
if (WriteEnable) begin
|
||||
StoredData[Addr] <= #1 WriteData;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign ReadData = StoredData[AddrD];
|
||||
|
||||
endmodule
|
||||
|
||||
/-* verilator lint_on ASSIGNDLY *-/
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
|
||||
// Depth is number of bits in one "word" of the memory, width is number of such words
|
||||
|
||||
/* verilator lint_off ASSIGNDLY */
|
||||
|
||||
module sram1rw #(parameter DEPTH=128, WIDTH=256) (
|
||||
input logic clk,
|
||||
// port 1 is read only
|
||||
input logic [$clog2(WIDTH)-1:0] Addr,
|
||||
output logic [DEPTH-1:0] ReadData,
|
||||
|
||||
// port 2 is write only
|
||||
input logic [DEPTH-1:0] WriteData,
|
||||
input logic WriteEnable
|
||||
);
|
||||
|
||||
logic [WIDTH-1:0][DEPTH-1:0] StoredData;
|
||||
logic [$clog2(WIDTH)-1:0] AddrD;
|
||||
logic [DEPTH-1:0] WriteDataD;
|
||||
logic [DEPTH-1:0][WIDTH-1:0] StoredData;
|
||||
logic [$clog2(DEPTH)-1:0] AddrD;
|
||||
logic [WIDTH-1:0] WriteDataD;
|
||||
logic WriteEnableD;
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
AddrD <= Addr;
|
||||
WriteDataD <= WriteData;
|
||||
WriteDataD <= WriteData; /// ****** this is not right. there should not need to be a delay.
|
||||
WriteEnableD <= WriteEnable;
|
||||
if (WriteEnableD) begin
|
||||
StoredData[AddrD] <= #1 WriteDataD;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign ReadData = StoredData[AddrD];
|
||||
|
||||
endmodule
|
||||
|
||||
/* verilator lint_on ASSIGNDLY */
|
||||
|
||||
|
|
|
|||
|
|
@ -49,7 +49,9 @@ module extend (
|
|||
else ExtImmD = undefined;
|
||||
default: begin
|
||||
ExtImmD = undefined; // undefined
|
||||
// synthesis translate_off
|
||||
$error("Invalid ImmSrcD in extend");
|
||||
// synthesis translate_on
|
||||
end
|
||||
endcase
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -31,11 +31,11 @@ module ifu (
|
|||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushF, FlushD, FlushE, FlushM, FlushW,
|
||||
// Bus interface
|
||||
input logic [`XLEN-1:0] IfuBusHRDATA,
|
||||
input logic IfuBusAck,
|
||||
output logic [`PA_BITS-1:0] IfuBusAdr,
|
||||
output logic IfuBusRead,
|
||||
output logic IfuStallF,
|
||||
(* mark_debug = "true" *) input logic [`XLEN-1:0] IfuBusHRDATA,
|
||||
(* mark_debug = "true" *) input logic IfuBusAck,
|
||||
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IfuBusAdr,
|
||||
(* mark_debug = "true" *) output logic IfuBusRead,
|
||||
(* mark_debug = "true" *) output logic IfuStallF,
|
||||
(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
|
||||
// Execute
|
||||
output logic [`XLEN-1:0] PCLinkE,
|
||||
|
|
@ -264,12 +264,12 @@ module ifu (
|
|||
.CacheMiss(),
|
||||
.CacheAccess(),
|
||||
.FinalWriteData('0),
|
||||
.RW(IfuRWF), //aways read
|
||||
.RW(IfuRWF),
|
||||
.Atomic(2'b00),
|
||||
.FlushCache(1'b0),
|
||||
.LsuAdrE(PCNextFMux), // fixme
|
||||
.LsuPAdrM(PCPF), // fixme
|
||||
.PreLsuPAdrM(PCFMux[11:0]), //fixme
|
||||
.NextAdr(PCNextFMux),
|
||||
.PAdr(PCPF),
|
||||
.NoTranAdr(PCFMux[11:0]),
|
||||
.CacheCommitted(),
|
||||
.InvalidateCacheM(InvalidateICacheM));
|
||||
|
||||
|
|
|
|||
|
|
@ -64,12 +64,12 @@ module lsu
|
|||
|
||||
// connect to ahb
|
||||
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] LsuBusAdr,
|
||||
output logic LsuBusRead,
|
||||
output logic LsuBusWrite,
|
||||
input logic LsuBusAck,
|
||||
(* mark_debug = "true" *) output logic LsuBusRead,
|
||||
(* mark_debug = "true" *) output logic LsuBusWrite,
|
||||
(* mark_debug = "true" *) input logic LsuBusAck,
|
||||
(* mark_debug = "true" *) input logic [`XLEN-1:0] LsuBusHRDATA,
|
||||
output logic [`XLEN-1:0] LsuBusHWDATA,
|
||||
output logic [2:0] LsuBusSize,
|
||||
(* mark_debug = "true" *) output logic [`XLEN-1:0] LsuBusHWDATA,
|
||||
(* mark_debug = "true" *) output logic [2:0] LsuBusSize,
|
||||
|
||||
// mmu management
|
||||
|
||||
|
|
@ -99,7 +99,7 @@ module lsu
|
|||
logic [1:0] PreLsuRWM;
|
||||
logic [2:0] LsuFunct3M;
|
||||
logic [1:0] LsuAtomicM;
|
||||
logic [`PA_BITS-1:0] PreLsuPAdrM, LocalLsuBusAdr;
|
||||
(* mark_debug = "true" *) logic [`PA_BITS-1:0] PreLsuPAdrM, LocalLsuBusAdr;
|
||||
logic [11:0] PreLsuAdrE, LsuAdrE;
|
||||
logic CPUBusy;
|
||||
logic MemReadM;
|
||||
|
|
@ -298,15 +298,16 @@ module lsu
|
|||
|
||||
if(`MEM_DCACHE) begin : dcache
|
||||
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
|
||||
.NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1))
|
||||
dcache(.clk, .reset, .CPUBusy,
|
||||
.RW(CacheableM ? LsuRWM : 2'b00), .FlushCache(FlushDCacheM), .Atomic(CacheableM ? LsuAtomicM : 2'b00),
|
||||
.LsuAdrE, .LsuPAdrM, .PreLsuPAdrM(PreLsuPAdrM[11:0]), // still don't like this name PreLsuPAdrM, not always physical
|
||||
.FinalWriteData(FinalWriteDataM), .ReadDataWord(ReadDataWordM), .CacheStall(DCacheStall),
|
||||
.CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
|
||||
.IgnoreRequest, .CacheCommitted(DCacheCommittedM),
|
||||
.CacheBusAdr(DCacheBusAdr), .ReadDataLineSets(ReadDataLineSetsM), .CacheMemWriteData(DCacheMemWriteData),
|
||||
.CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));
|
||||
.NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1))
|
||||
dcache(.clk, .reset, .CPUBusy,
|
||||
.RW(CacheableM ? LsuRWM : 2'b00), .FlushCache(FlushDCacheM), .Atomic(CacheableM ? LsuAtomicM : 2'b00),
|
||||
.NextAdr(LsuAdrE), .PAdr(LsuPAdrM), .NoTranAdr(PreLsuPAdrM[11:0]),
|
||||
.FinalWriteData(FinalWriteDataM), .ReadDataWord(ReadDataWordM), .CacheStall(DCacheStall),
|
||||
.CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
|
||||
.IgnoreRequest, .CacheCommitted(DCacheCommittedM),
|
||||
.CacheBusAdr(DCacheBusAdr), .ReadDataLineSets(ReadDataLineSetsM), .CacheMemWriteData(DCacheMemWriteData),
|
||||
.CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));
|
||||
|
||||
end else begin : passthrough
|
||||
assign ReadDataWordM = 0;
|
||||
assign DCacheStall = 0;
|
||||
|
|
|
|||
|
|
@ -279,7 +279,7 @@ module testbench;
|
|||
end
|
||||
|
||||
`INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1);
|
||||
`INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,3);
|
||||
`INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,0);
|
||||
`INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]);
|
||||
|
|
|
|||
|
|
@ -349,8 +349,8 @@ read32_test:
|
|||
li x7, 0xBAD # bad value that will be overwritten on good reads.
|
||||
lw x7, 0(x28)
|
||||
sw x7, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
addi x6, x6, 4
|
||||
addi x16, x16, 4
|
||||
j test_loop # go to next test case
|
||||
|
||||
read16_test:
|
||||
|
|
@ -358,8 +358,8 @@ read16_test:
|
|||
li x7, 0xBAD # bad value that will be overwritten on good reads.
|
||||
lh x7, 0(x28)
|
||||
sw x7, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
addi x6, x6, 4
|
||||
addi x16, x16, 4
|
||||
j test_loop # go to next test case
|
||||
|
||||
read08_test:
|
||||
|
|
@ -367,8 +367,8 @@ read08_test:
|
|||
li x7, 0xBAD # bad value that will be overwritten on good reads.
|
||||
lb x7, 0(x28)
|
||||
sw x7, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
addi x6, x6, 4
|
||||
addi x16, x16, 4
|
||||
j test_loop # go to next test case
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue