mirror of
https://github.com/openhwgroup/cvw.git
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
This commit is contained in:
David Harris
commit
f12cdf55fe
3 changed files with 15 additions and 19 deletions
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@ -90,7 +90,7 @@ RTL_FILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/mem/
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# Simulation and Coverage Commands
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OUTPUT="sim_out"
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VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF +vcs+vcdpluson -suppress +warn -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -ntb_opts sensitive_dyn +define+SIM_VCS ${INCLUDE_PATH} $RTL_FILES"
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VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF +vcs+vcdpluson -suppress +warn -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -ntb_opts sensitive_dyn ${INCLUDE_PATH} $RTL_FILES"
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SIMV_CMD="./${WKDIR}/$OUTPUT +TEST=${TESTSUITE} ${PLUSARGS}"
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COV_FILES="${TB}/coverage/test_pmp_coverage.sv"
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COV_OPTIONS="-cm line+cond+branch+fsm+tgl -cm_log ${WKDIR}/coverage.log -cm_dir ${WKDIR}/COVERAGE"
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@ -54,7 +54,7 @@ module testbench;
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`ifdef VERILATOR
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import "DPI-C" function string getenvval(input string env_name);
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string RISCV_DIR = getenvval("RISCV"); // "/opt/riscv";
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`elsif SIM_VCS
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`elsif VCS
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import "DPI-C" function string getenv(input string env_name);
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string RISCV_DIR = getenv("RISCV"); // "/opt/riscv";
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`else
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@ -419,12 +419,10 @@ module testbench;
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$display("Coverage tests don't get checked");
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end else if (ElfFile != "none") begin
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$display("Single Elf file tests are not signatured verified.");
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`ifdef VERILATOR // this macro is defined when verilator is used
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$finish; // Simulator Verilator needs $finish to terminate simulation.
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`elsif SIM_VCS // this macro is defined when vcs is used
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$finish; // Simulator VCS needs $finish to terminate simulation.
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`ifdef QUESTA
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$stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
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`else
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$stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
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$finish;
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`endif
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end else begin
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// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
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@ -440,12 +438,10 @@ module testbench;
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if (test == tests.size()) begin
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if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
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else $display("FAIL: %d test programs had errors", totalerrors);
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`ifdef VERILATOR // this macro is defined when verilator is used
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$finish; // Simulator Verilator needs $finish to terminate simulation.
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`elsif SIM_VCS // this macro is defined when vcs is used
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$finish; // Simulator VCS needs $finish to terminate simulation.
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`ifdef QUESTA
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$stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
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`else
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$stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
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$finish;
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`endif
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end
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end
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@ -1083,7 +1083,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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end
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Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
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end
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2'b00: if (P.S_SUPPORTED) begin // single
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2'b00: if (P.F_SUPPORTED) begin // single
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if (OpCtrl === `FMA_OPCTRL) begin
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X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+4*(P.S_LEN)-1:8+3*(P.S_LEN)]};
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Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
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@ -1125,7 +1125,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
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Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
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end
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2'b00: if (P.S_SUPPORTED) begin // single
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2'b00: if (P.F_SUPPORTED) begin // single
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X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
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Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
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end
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@ -1146,7 +1146,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
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Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
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end
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2'b00: if (P.S_SUPPORTED) begin // single
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2'b00: if (P.F_SUPPORTED) begin // single
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X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
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Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
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Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
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@ -1169,7 +1169,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]};
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Ans = {{P.FLEN-1{1'b0}}, TestVector[8]};
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end
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2'b00: if (P.S_SUPPORTED) begin // single
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2'b00: if (P.F_SUPPORTED) begin // single
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X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]};
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Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]};
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Ans = {{P.FLEN-1{1'b0}}, TestVector[8]};
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@ -1222,7 +1222,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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end
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endcase
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end
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2'b00: if (P.S_SUPPORTED) begin // single
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2'b00: if (P.F_SUPPORTED) begin // single
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case (OpCtrl[1:0])
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2'b11: begin // quad
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X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
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@ -1252,7 +1252,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.D_LEN-1:8+(P.D_LEN)]};
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Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
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end
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2'b00: if (P.S_SUPPORTED) begin // single
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2'b00: if (P.F_SUPPORTED) begin // single
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X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.S_LEN-1:8+(P.S_LEN)]};
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Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
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end
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@ -1317,7 +1317,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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end
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endcase
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end
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2'b00: if (P.S_SUPPORTED) begin // single
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2'b00: if (P.F_SUPPORTED) begin // single
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// {is the integer a long, is the opperation to an integer}
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casez ({OpCtrl[2:1]})
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2'b11: begin // long -> single
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