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Modified fpga config to support two fpga boards with different amount of memory.

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Modified vcu108 constraints to better constrain the spi clock and in/out.
This commit is contained in:
Rose Thompson 2024-08-29 16:12:58 -07:00
parent cb05697698
commit f1d9e18dee
5 changed files with 29 additions and 16 deletions
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9
fpga/src/fpgaTop.sv
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@ -182,6 +182,7 @@ module fpgaTop
logic [511 : 0] dbg_bus;
logic CLK208;
logic SDCCLKInternal;
assign GPIOIN = {25'b0, SDCCD, SDCWP, 2'b0, GPI};
assign GPO = GPIOOUT[4:0];
@ -215,8 +216,12 @@ module fpgaTop
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0),
.GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall));
.UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK(SDCCLKInternal), .ExternalStall(RVVIStall));
// *** these are different for different fpga ugh.
ODDRE1 sdcclkoddr(.Q(SDCCLK), .C(SDCCLKInternal), .D1('0),
.D2(1'b1), .SR('0));
// ahb lite to axi bridge
ahbaxibridge ahbaxibridge
(.s_ahb_hclk(CPUCLK),