github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-04-22 12:57:23 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Finished UART test

Browse source
This commit is contained in:
David Harris 2022-07-27 04:06:59 +00:00
parent da275e3c26
commit f61f0645fe
2 changed files with 6 additions and 43 deletions
Download patch file Download diff file Expand all files Collapse all files

27
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-uart-01.reference_output
View file

@ -62,27 +62,8 @@ ffffffC1 # Threshold = 8
ffffffC1 # Threshold = 14
0000C101
0000C401
0000C401
00000061
00000006
00000063
00000000
00000001
0000C401
00000061
00000002
00000003
00000004
00000005
00000006
00000007
00000008
00000009
0000000A
0000000B
0000000C
0000000D
0000000E
0000000F
0000C201
00000061 # FIFO has data, no overrun
00000006 # wait for interrupt
000000A3 # FIFO overrun error
0000000b # ecall from test termination

22
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S
View file

@ -216,29 +216,11 @@ test_cases:
.4byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached
.4byte UART_THR, 0x0E, write08_test # Write 14 to transmit register
.4byte UART_THR, 0x0F, write08_test # Write 15 to transmit register
.4byte 0x0, 0xC401, uart_data_wait
.4byte 0x0, 0xC201, uart_data_wait
.4byte UART_LSR, 0x61, read08_test # FIFO contains data, no overrun error
.4byte UART_THR, 0x10, write08_test # Write 16 to transmit register, filling RX shift register
.4byte UART_THR, 0x11, write08_test # Write 17 to transmit register, destroying contents held in shift register
.4byte 0x0, 0x06, uart_lsr_intr_wait # Wait for LSR interrupt ID
.4byte UART_LSR, 0x63, read08_test # Read overrun error from LSR
.4byte UART_RBR, 0x00, read08_test # Read 0 from FIFO
.4byte UART_RBR, 0x01, read08_test # Read 1 from FIFO
.4byte UART_THR, 0x12, write08_test # Write 18 to transmit register, showing space in FIFO
.4byte 0x0, 0x0401, uart_data_wait
.4byte UART_RBR, 0x02, read08_test # Read 2 from FIFO
.4byte UART_RBR, 0x03, read08_test # Read 3 from FIFO
.4byte UART_RBR, 0x04, read08_test # Read 4 from FIFO
.4byte UART_RBR, 0x05, read08_test # Read 5 from FIFO
.4byte UART_RBR, 0x06, read08_test # Read 6 from FIFO
.4byte UART_RBR, 0x07, read08_test # Read 7 from FIFO
.4byte UART_RBR, 0x08, read08_test # Read 8 from FIFO
.4byte UART_RBR, 0x09, read08_test # Read 9 from FIFO
.4byte UART_RBR, 0x0A, read08_test # Read 10 from FIFO
.4byte UART_RBR, 0x0B, read08_test # Read 11 from FIFO
.4byte UART_RBR, 0x0C, read08_test # Read 12 from FIFO
.4byte UART_RBR, 0x0D, read08_test # Read 13 from FIFO
.4byte UART_RBR, 0x0E, read08_test # Read 14 from FIFO
.4byte UART_RBR, 0x0F, read08_test # Read 15 from FIFO
.4byte UART_LSR, 0xA3, read08_test # Read overrun error from LSR
.4byte 0x0, 0x0, terminate_test