github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-04-24 22:07:12 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

Added performance new counter prints to testbench.

Browse source
This commit is contained in:
Ross Thompson 2023-03-03 10:42:52 -06:00
parent 17adba5fd5
commit f6e97cf516
1 changed files with 125 additions and 136 deletions
Download patch file Download diff file Expand all files Collapse all files

45
testbench/testbench.sv
View file

@ -268,9 +268,6 @@ logic [3:0] dummy;
// if ($time % 100000 == 0) $display("Time is %0t", $time);
end
logic [`XLEN-1:0] debugmemoryadr;
// assign debugmemoryadr = dut.uncore.uncore.ram.ram.memory.RAM[5140];
// check results
assign reset_ext = InReset;
@ -409,19 +406,29 @@ logic [3:0] dummy;
string HPMCnames[] = '{"Mcycle",
"------",
"InstRet",
"Load Stall",
"Br Dir Wrong",
"Br Count",
"Br Target Wrong",
"Jump, JR, Jal",
"Return",
"Br Dir Wrong",
"Br Pred Wrong",
"Br Target Wrong",
"RAS Wrong",
"ret",
"Instr Class Wrong",
"Load Stall",
"Store Stall",
"D Cache Access",
"D Cache Miss",
"D Cache Cycles",
"I Cache Access",
"I Cache Miss",
"Br Pred Wrong"};
"I Cache Cycles",
"CSR Write",
"FenceI",
"SFenceVMA",
"Interrupt",
"Exception",
"Divide Cycles"
};
always @(negedge clk) begin
if(DCacheFlushStart & ~DCacheFlushDone) begin
for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
@ -487,32 +494,14 @@ logic [3:0] dummy;
if (`BPRED_SUPPORTED == 1) begin
/* -----\/----- EXCLUDED -----\/-----
genvar adrindex;
// Initializing all zeroes into the branch predictor memory.
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
initial begin
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
#1;
release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
end
end
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
initial begin
force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
#1;
release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
end
end
-----/\----- EXCLUDED -----/\----- */
if (`BPRED_LOGGER) begin
string direction;
int file;
logic PCSrcM;
flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
initial
initial begin
file = $fopen("branch.log", "w");
end
always @(posedge clk) begin
if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
direction = PCSrcM ? "t" : "n";