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Fixed bugs in the updated fpga synthe script.

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This commit is contained in:
Rose Thompson 2023-11-13 18:10:22 -06:00
parent d5f0c15b90
commit f8b65f50b0
2 changed files with 11 additions and 11 deletions
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20
fpga/generator/Makefile
View file

@ -6,20 +6,20 @@ dst := IP
#export board := vcu118
# vcu108
export XILINX_PART := xcvu095-ffva2104-2-e
export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
export board := vcu108
#export XILINX_PART := xcvu095-ffva2104-2-e
#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
#export board := vcu108
# Arty A7
# export XILINX_PART := xc7a100tcsg324-1
# export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
# export board := ArtyA7
export XILINX_PART := xc7a100tcsg324-1
export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
export board := ArtyA7
# for Arty A7 and S7 boards
# all: FPGA_Arty
all: FPGA_Arty
# VCU 108 and VCU 118 boards
all: FPGA_VCU
#all: FPGA_VCU
FPGA_Arty: PreProcessFiles IP_Arty
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
@ -63,11 +63,11 @@ PreProcessFiles:
sed -i "s/EXT_MEM_SUPPORTED.*/EXT_MEM_SUPPORTED = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/SDC_SUPPORTED.*/SDC_SUPPORTED = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/SPI_SUPPORTED.*/SDC_SUPPORTED = 1'b0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh # *** RT: Add SPI when ready
sed -i "s/SPI_SUPPORTED.*/SPI_SUPPORTED = 1'b0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh # *** RT: Add SPI when ready
sed -i "s/GPIO_LOOPBACK_TEST.*/GPIO_LOOPBACK_TEST = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/SPI_LOOPBACK_TEST.*/SPI_LOOPBACK_TEST = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/UART_PRESCALE.*/UART_PRESCALE = 32'd0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/PLIC_NUM_SRC.*/PLIC_NUM_SRC = 32'd53;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/PLIC_NUM_SRC = .*/PLIC_NUM_SRC = 32'd53;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/PLIC_SDC_ID.*/PLIC_SDC_ID = 32'd20;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/BPRED_SIZE.*/BPRED_SIZE = 32'd12;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh

2
fpga/generator/wally.tcl
View file

@ -48,7 +48,7 @@ read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_cmd_serial_host.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_master.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_serial_host.v]
set_property include_dirs {../src/CopiedFiles_do_no_add_to_repo/config/ ../../config/shared ../../addins/vivado-risc-v/sdc} [current_fileset]
set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/vivado-risc-v/sdc} [current_fileset]
if {$board=="ArtyA7"} {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc