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Initial commit for the boot process.

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This commit is contained in:
Jacob Pease 2023-01-10 11:19:28 -06:00
parent e3df1d3326
commit fa087aeb30
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4
pipelined/config/fpga/wally-config.vh
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`define SDC_BASE 56'h00012100
`define SDC_RANGE 56'h0000001F
// Temporary Boot Process Stuff
`define SDC2_BASE 56'h00013000
`defube SDC2_RANGE 56'h0000007F
// Bus Interface width
`define AHBW 64

661
pipelined/src/uncore/newsdc/axi_sdc_controller.v Normal file
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@ -0,0 +1,661 @@
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013-2022 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from https://www.gnu.org/licenses/ ////
//// ////
//////////////////////////////////////////////////////////////////////
module sdc_controller #(
parameter dma_addr_bits = 32,
parameter fifo_addr_bits = 7,
parameter sdio_card_detect_level = 1,
parameter voltage_controll_reg = 3300,
parameter capabilies_reg = 16'b0000_0000_0000_0011
) (
input wire async_resetn,
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK" *)
(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF M_AXI:S_AXI_LITE, FREQ_HZ 100000000" *)
input wire clock,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *)
(* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32" *)
input wire [15:0] s_axi_awaddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *)
input wire s_axi_awvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *)
output wire s_axi_awready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *)
input wire [31:0] s_axi_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *)
input wire s_axi_wvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *)
output wire s_axi_wready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *)
output reg [1:0] s_axi_bresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *)
output reg s_axi_bvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *)
input wire s_axi_bready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *)
input wire [15:0] s_axi_araddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *)
input wire s_axi_arvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *)
output wire s_axi_arready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *)
output reg [31:0] s_axi_rdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *)
output reg [1:0] s_axi_rresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *)
output reg s_axi_rvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *)
input wire s_axi_rready,
(* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4, DATA_WIDTH 32" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output reg [dma_addr_bits-1:0] m_axi_awaddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output reg [7:0] m_axi_awlen,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output reg m_axi_awvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31:0] m_axi_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output reg m_axi_wlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output reg m_axi_wvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1:0] m_axi_bresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output reg [dma_addr_bits-1:0] m_axi_araddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output reg [7:0] m_axi_arlen,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output reg m_axi_arvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31:0] m_axi_rdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1:0] m_axi_rresp,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready,
// SD BUS
inout wire sdio_cmd,
inout wire [3:0] sdio_dat,
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 sdio_clk CLK" *)
(* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *)
output reg sdio_clk,
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 sdio_reset RST" *)
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
output reg sdio_reset,
input wire sdio_cd,
// Interrupts
output wire interrupt
);
`include "sd_defines.h"
wire reset;
wire go_idle;
reg cmd_start;
wire [1:0] cmd_setting;
wire cmd_start_tx;
wire [39:0] cmd;
wire [119:0] cmd_response;
wire cmd_crc_ok;
wire cmd_index_ok;
wire cmd_finish;
wire d_write;
wire d_read;
wire [31:0] data_in_rx_fifo;
wire en_tx_fifo;
wire en_rx_fifo;
wire sd_data_busy;
wire data_busy;
wire data_crc_ok;
wire tx_fifo_re;
wire rx_fifo_we;
reg data_start_rx;
reg data_start_tx;
reg data_prepare_tx;
reg cmd_int_rst;
reg data_int_rst;
reg ctrl_rst;
// AXI accessible registers
reg [31:0] argument_reg;
reg [`CMD_REG_SIZE-1:0] command_reg;
reg [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg;
reg [`DATA_TIMEOUT_W-1:0] data_timeout_reg;
reg [0:0] software_reset_reg;
wire [31:0] response_0_reg;
wire [31:0] response_1_reg;
wire [31:0] response_2_reg;
wire [31:0] response_3_reg;
reg [`BLKSIZE_W-1:0] block_size_reg;
reg [1:0] controller_setting_reg;
wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg;
wire [`INT_DATA_SIZE-1:0] data_int_status_reg;
wire [`INT_DATA_SIZE-1:0] data_int_status;
reg [`INT_CMD_SIZE-1:0] cmd_int_enable_reg;
reg [`INT_DATA_SIZE-1:0] data_int_enable_reg;
reg [`BLKCNT_W-1:0] block_count_reg;
reg [dma_addr_bits-1:0] dma_addr_reg;
reg [7:0] clock_divider_reg = 124; // 400KHz
// ------ Clocks and resets
(* ASYNC_REG="true" *)
reg [2:0] reset_sync;
assign reset = reset_sync[2];
always @(posedge clock)
reset_sync <= {reset_sync[1:0], !async_resetn};
reg [7:0] clock_cnt;
reg clock_state;
reg clock_posedge;
reg clock_data_in;
wire fifo_almost_full;
wire fifo_almost_empty;
always @(posedge clock) begin
if (reset) begin
clock_posedge <= 0;
clock_data_in <= 0;
clock_state <= 0;
clock_cnt <= 0;
end else if (clock_cnt < clock_divider_reg) begin
clock_posedge <= 0;
clock_data_in <= 0;
clock_cnt <= clock_cnt + 1;
end else if (clock_cnt < 124 && data_busy && en_rx_fifo && fifo_almost_full) begin
// Prevent Rx FIFO overflow
clock_posedge <= 0;
clock_data_in <= 0;
clock_cnt <= clock_cnt + 1;
end else if (clock_cnt < 124 && data_busy && en_tx_fifo && fifo_almost_empty) begin
// Prevent Tx FIFO underflow
clock_posedge <= 0;
clock_data_in <= 0;
clock_cnt <= clock_cnt + 1;
end else begin
clock_state <= !clock_state;
clock_posedge <= !clock_state;
if (clock_divider_reg == 0)
clock_data_in <= !clock_state;
else
clock_data_in <= clock_state;
clock_cnt <= 0;
end
sdio_clk <= sdio_reset || clock_state;
if (reset) sdio_reset <= 0;
else if (clock_posedge) sdio_reset <= controller_setting_reg[1];
end
// ------ SD IO Buffers
wire sd_cmd_i;
wire sd_cmd_o;
wire sd_cmd_oe;
reg sd_cmd_reg_o;
reg sd_cmd_reg_t;
wire [3:0] sd_dat_i;
wire [3:0] sd_dat_o;
wire sd_dat_oe;
reg [3:0] sd_dat_reg_o;
reg sd_dat_reg_t;
IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t));
IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t));
IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t));
IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t));
IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t));
always @(negedge clock) begin
// Output data delayed by 1/2 clock cycle (5ns) to ensure
// required hold time: default speed - min 5ns, high speed - min 2ns (actual 5ns)
if (sdio_reset) begin
sd_cmd_reg_o <= 0;
sd_dat_reg_o <= 0;
sd_cmd_reg_t <= 0;
sd_dat_reg_t <= 0;
end else begin
sd_cmd_reg_o <= sd_cmd_o;
sd_dat_reg_o <= sd_dat_o;
sd_cmd_reg_t <= !sd_cmd_oe;
sd_dat_reg_t <= !(sd_dat_oe || (cmd_start_tx && (command_reg == 0)));
end
end
// ------ SD card detect
reg [25:0] sd_detect_cnt;
wire sd_insert_int = sd_detect_cnt[25];
wire sd_remove_int = !sd_detect_cnt[25];
reg sd_insert_ie;
reg sd_remove_ie;
always @(posedge clock) begin
if (sdio_cd != sdio_card_detect_level) begin
sd_detect_cnt <= 0;
end else if (!sd_insert_int) begin
sd_detect_cnt <= sd_detect_cnt + 1;
end
end
// ------ AXI Slave Interface
reg [15:0] read_addr;
reg [15:0] write_addr;
reg [31:0] write_data;
reg rd_req;
reg [1:0] wr_req;
assign s_axi_arready = !rd_req && !s_axi_rvalid;
assign s_axi_awready = !wr_req[0] && !s_axi_bvalid;
assign s_axi_wready = !wr_req[1] && !s_axi_bvalid;
always @(posedge clock) begin
if (reset) begin
s_axi_rdata <= 0;
s_axi_rresp <= 0;
s_axi_rvalid <= 0;
s_axi_bresp <= 0;
s_axi_bvalid <= 0;
rd_req <= 0;
wr_req <= 0;
read_addr <= 0;
write_addr <= 0;
write_data <= 0;
cmd_start <= 0;
data_int_rst <= 0;
cmd_int_rst <= 0;
ctrl_rst <= 0;
argument_reg <= 0;
command_reg <= 0;
cmd_timeout_reg <= 0;
data_timeout_reg <= 0;
block_size_reg <= `RESET_BLOCK_SIZE;
controller_setting_reg <= 0;
cmd_int_enable_reg <= 0;
data_int_enable_reg <= 0;
software_reset_reg <= 0;
clock_divider_reg <= `RESET_CLOCK_DIV;
block_count_reg <= 0;
sd_insert_ie <= 0;
sd_remove_ie <= 0;
dma_addr_reg <= 0;
end else begin
if (clock_posedge) begin
cmd_start <= 0;
data_int_rst <= 0;
cmd_int_rst <= 0;
ctrl_rst <= software_reset_reg[0];
end
if (s_axi_arready && s_axi_arvalid) begin
read_addr <= s_axi_araddr;
rd_req <= 1;
end
if (s_axi_rvalid && s_axi_rready) begin
s_axi_rvalid <= 0;
end else if (!s_axi_rvalid && rd_req) begin
s_axi_rdata <= 0;
if (read_addr[15:8] == 0) begin
case (read_addr[7:0])
`argument : s_axi_rdata <= argument_reg;
`command : s_axi_rdata <= command_reg;
`resp0 : s_axi_rdata <= response_0_reg;
`resp1 : s_axi_rdata <= response_1_reg;
`resp2 : s_axi_rdata <= response_2_reg;
`resp3 : s_axi_rdata <= response_3_reg;
`controller : s_axi_rdata <= controller_setting_reg;
`blksize : s_axi_rdata <= block_size_reg;
`voltage : s_axi_rdata <= voltage_controll_reg;
`capa : s_axi_rdata <= capabilies_reg | (dma_addr_bits << 8);
`clock_d : s_axi_rdata <= clock_divider_reg;
`reset : s_axi_rdata <= { cmd_start, data_int_rst, cmd_int_rst, ctrl_rst };
`cmd_timeout : s_axi_rdata <= cmd_timeout_reg;
`data_timeout : s_axi_rdata <= data_timeout_reg;
`cmd_isr : s_axi_rdata <= cmd_int_status_reg;
`cmd_iser : s_axi_rdata <= cmd_int_enable_reg;
`data_isr : s_axi_rdata <= data_int_status_reg;
`data_iser : s_axi_rdata <= data_int_enable_reg;
`blkcnt : s_axi_rdata <= block_count_reg;
`card_detect : s_axi_rdata <= { sd_remove_int, sd_remove_ie, sd_insert_int, sd_insert_ie };
`dst_src_addr : s_axi_rdata <= dma_addr_reg[31:0];
`dst_src_addr_high : if (dma_addr_bits > 32) s_axi_rdata <= dma_addr_reg[dma_addr_bits-1:32];
endcase
end
s_axi_rresp <= 0;
s_axi_rvalid <= 1;
rd_req <= 0;
end
if (s_axi_awready && s_axi_awvalid) begin
write_addr <= s_axi_awaddr;
wr_req[0] <= 1;
end
if (s_axi_wready && s_axi_wvalid) begin
write_data <= s_axi_wdata;
wr_req[1] <= 1;
end
if (s_axi_bvalid && s_axi_bready) begin
s_axi_bvalid <= 0;
end else if (!s_axi_bvalid && wr_req == 2'b11) begin
if (write_addr[15:8] == 0) begin
case (write_addr[7:0])
`argument : begin argument_reg <= write_data; cmd_start <= 1; end
`command : command_reg <= write_data;
`reset : software_reset_reg <= write_data;
`cmd_timeout : cmd_timeout_reg <= write_data;
`data_timeout : data_timeout_reg <= write_data;
`blksize : block_size_reg <= write_data;
`controller : controller_setting_reg <= write_data;
`cmd_isr : cmd_int_rst <= 1;
`cmd_iser : cmd_int_enable_reg <= write_data;
`clock_d : clock_divider_reg <= write_data;
`data_isr : data_int_rst <= 1;
`data_iser : data_int_enable_reg <= write_data;
`blkcnt : block_count_reg <= write_data;
`card_detect : begin sd_remove_ie <= write_data[2]; sd_insert_ie <= write_data[0]; end
`dst_src_addr : dma_addr_reg[31:0] <= write_data;
`dst_src_addr_high : if (dma_addr_bits > 32) dma_addr_reg[dma_addr_bits-1:32] <= write_data;
endcase
end
s_axi_bresp <= 0;
s_axi_bvalid <= 1;
wr_req <= 0;
end
end
end
// ------ Data FIFO
reg [31:0] fifo_mem [(1<<fifo_addr_bits)-1:0];
reg [fifo_addr_bits-1:0] fifo_inp_pos;
reg [fifo_addr_bits-1:0] fifo_out_pos;
wire [fifo_addr_bits-1:0] fifo_inp_nxt = fifo_inp_pos + 1;
wire [fifo_addr_bits-1:0] fifo_out_nxt = fifo_out_pos + 1;
wire [fifo_addr_bits-1:0] fifo_data_len = fifo_inp_pos - fifo_out_pos;
wire [fifo_addr_bits-1:0] fifo_free_len = fifo_out_pos - fifo_inp_nxt;
wire fifo_full = fifo_inp_nxt == fifo_out_pos;
wire fifo_empty = fifo_inp_pos == fifo_out_pos;
wire fifo_ready = fifo_data_len >= (1 << fifo_addr_bits) / 2;
wire [31:0] fifo_din = en_rx_fifo ? data_in_rx_fifo : m_bus_dat_i;
wire fifo_we = en_rx_fifo ? rx_fifo_we && clock_posedge : m_axi_rready && m_axi_rvalid;
wire fifo_re = en_rx_fifo ? m_axi_wready && m_axi_wvalid : tx_fifo_re && clock_posedge;
reg [31:0] fifo_dout;
assign fifo_almost_full = fifo_data_len > (1 << fifo_addr_bits) * 3 / 4;
assign fifo_almost_empty = fifo_free_len > (1 << fifo_addr_bits) * 3 / 4;
wire tx_stb = en_tx_fifo && fifo_free_len >= (1 << fifo_addr_bits) / 3;
wire rx_stb = en_rx_fifo && m_axi_bresp_cnt != 3'b111 && (fifo_data_len >= (1 << fifo_addr_bits) / 3 || (!fifo_empty && !data_busy));
always @(posedge clock)
if (reset || ctrl_rst || !(en_rx_fifo || en_tx_fifo)) begin
fifo_inp_pos <= 0;
fifo_out_pos <= 0;
end else begin
if (fifo_we && !fifo_full) begin
fifo_mem[fifo_inp_pos] <= fifo_din;
fifo_inp_pos <= fifo_inp_nxt;
if (fifo_empty) fifo_dout <= fifo_din;
end
if (fifo_re && !fifo_empty) begin
if (fifo_we && !fifo_full && fifo_out_nxt == fifo_inp_pos) fifo_dout <= fifo_din;
else fifo_dout <= fifo_mem[fifo_out_nxt];
fifo_out_pos <= fifo_out_nxt;
end
end
// ------ AXI Master Interface
// AXI transaction (DDR access) is over 80 clock cycles
// Must use burst to achive required throughput
reg m_axi_cyc;
wire m_axi_write = en_rx_fifo;
reg [7:0] m_axi_wcnt;
reg [dma_addr_bits-1:2] m_bus_adr_o;
wire [31:0] m_bus_dat_i;
reg [2:0] m_axi_bresp_cnt;
reg m_bus_error;
assign m_axi_bready = m_axi_bresp_cnt != 0;
assign m_axi_rready = m_axi_cyc & !m_axi_write;
assign m_bus_dat_i = {m_axi_rdata[7:0],m_axi_rdata[15:8],m_axi_rdata[23:16],m_axi_rdata[31:24]};
assign m_axi_wdata = {fifo_dout[7:0],fifo_dout[15:8],fifo_dout[23:16],fifo_dout[31:24]};
// AXI burst cannot cross a 4KB boundary
wire [fifo_addr_bits-1:0] tx_burst_len;
wire [fifo_addr_bits-1:0] rx_burst_len;
assign tx_burst_len = m_bus_adr_o[11:2] + fifo_free_len >= m_bus_adr_o[11:2] ? fifo_free_len - 1 : ~m_bus_adr_o[fifo_addr_bits+1:2];
assign rx_burst_len = m_bus_adr_o[11:2] + fifo_data_len >= m_bus_adr_o[11:2] ? fifo_data_len - 1 : ~m_bus_adr_o[fifo_addr_bits+1:2];
assign data_int_status_reg = { data_int_status[`INT_DATA_SIZE-1:1],
!en_rx_fifo && !en_tx_fifo && !m_axi_cyc && m_axi_bresp_cnt == 0 && data_int_status[0] };
always @(posedge clock) begin
if (reset | ctrl_rst) begin
m_axi_arvalid <= 0;
m_axi_awvalid <= 0;
m_axi_wvalid <= 0;
m_axi_cyc <= 0;
end else if (m_axi_cyc) begin
if (m_axi_awvalid && m_axi_awready) begin
m_axi_awvalid <= 0;
end
if (m_axi_arvalid && m_axi_arready) begin
m_axi_arvalid <= 0;
end
if (m_axi_wvalid && m_axi_wready) begin
if (m_axi_wlast) begin
m_axi_wvalid <= 0;
m_axi_cyc <= 0;
end else begin
m_axi_wlast <= m_axi_wcnt + 1 == m_axi_awlen;
m_axi_wcnt <= m_axi_wcnt + 1;
end
end
if (m_axi_rvalid && m_axi_rready && m_axi_rlast) begin
m_axi_cyc <= 0;
end
end else if (tx_stb || rx_stb) begin
m_axi_cyc <= 1;
m_axi_wcnt <= 0;
if (m_axi_write) begin
m_axi_awaddr <= { m_bus_adr_o, 2'b00 };
m_axi_awlen <= rx_burst_len < 8'hff ? rx_burst_len : 8'hff;
m_axi_wlast <= rx_burst_len == 0;
m_axi_awvalid <= 1;
m_axi_wvalid <= 1;
end else begin
m_axi_araddr <= { m_bus_adr_o, 2'b00 };
m_axi_arlen <= tx_burst_len < 8'hff ? tx_burst_len : 8'hff;
m_axi_arvalid <= 1;
end
end
if (reset | ctrl_rst) begin
m_bus_adr_o <= 0;
end else if ((m_axi_wready && m_axi_wvalid) || (m_axi_rready && m_axi_rvalid)) begin
m_bus_adr_o <= m_bus_adr_o + 1;
end else if (!m_axi_cyc && !en_rx_fifo && !en_tx_fifo) begin
m_bus_adr_o <= dma_addr_reg[dma_addr_bits-1:2];
end
if (reset | ctrl_rst) begin
m_axi_bresp_cnt <= 0;
end else if ((m_axi_awvalid && m_axi_awready) && !(m_axi_bvalid && m_axi_bready)) begin
m_axi_bresp_cnt <= m_axi_bresp_cnt + 1;
end else if (!(m_axi_awvalid && m_axi_awready) && (m_axi_bvalid && m_axi_bready)) begin
m_axi_bresp_cnt <= m_axi_bresp_cnt - 1;
end
if (reset | ctrl_rst | cmd_start) begin
m_bus_error <= 0;
end else if (m_axi_bvalid && m_axi_bready && m_axi_bresp) begin
m_bus_error <= 1;
end else if (m_axi_rvalid && m_axi_rready && m_axi_rresp) begin
m_bus_error <= 1;
end
if (reset | ctrl_rst) begin
data_start_tx <= 0;
data_start_rx <= 0;
data_prepare_tx <= 0;
end else if (clock_posedge) begin
data_start_tx <= 0;
data_start_rx <= 0;
if (cmd_start) begin
data_prepare_tx <= 0;
if (command_reg[`CMD_WITH_DATA] == 2'b01) data_start_rx <= 1;
else if (command_reg[`CMD_WITH_DATA] != 2'b00) data_prepare_tx <= 1;
end else if (data_prepare_tx) begin
if (cmd_int_status_reg[`INT_CMD_CC]) begin
data_prepare_tx <= 0;
data_start_tx <= 1;
end else if (cmd_int_status_reg[`INT_CMD_EI]) begin
data_prepare_tx <= 0;
end
end
end
end
// ------ SD Card Interface
sd_cmd_master sd_cmd_master0(
.clock (clock),
.clock_posedge (clock_posedge),
.reset (reset | ctrl_rst),
.start (cmd_start),
.int_status_rst (cmd_int_rst),
.setting (cmd_setting),
.start_xfr (cmd_start_tx),
.go_idle (go_idle),
.cmd (cmd),
.response (cmd_response),
.crc_error (!cmd_crc_ok),
.index_ok (cmd_index_ok),
.busy (sd_data_busy),
.finish (cmd_finish),
.argument (argument_reg),
.command (command_reg),
.timeout (cmd_timeout_reg),
.int_status (cmd_int_status_reg),
.response_0 (response_0_reg),
.response_1 (response_1_reg),
.response_2 (response_2_reg),
.response_3 (response_3_reg)
);
sd_cmd_serial_host cmd_serial_host0(
.clock (clock),
.clock_posedge (clock_posedge),
.clock_data_in (clock_data_in),
.reset (reset | ctrl_rst | go_idle),
.setting (cmd_setting),
.cmd (cmd),
.start (cmd_start_tx),
.finish (cmd_finish),
.response (cmd_response),
.crc_ok (cmd_crc_ok),
.index_ok (cmd_index_ok),
.cmd_i (sd_cmd_i),
.cmd_o (sd_cmd_o),
.cmd_oe (sd_cmd_oe)
);
sd_data_master sd_data_master0(
.clock (clock),
.clock_posedge (clock_posedge),
.reset (reset | ctrl_rst),
.start_tx (data_start_tx),
.start_rx (data_start_rx),
.timeout (data_timeout_reg),
.d_write (d_write),
.d_read (d_read),
.en_tx_fifo (en_tx_fifo),
.en_rx_fifo (en_rx_fifo),
.fifo_empty (fifo_empty),
.fifo_ready (fifo_ready),
.fifo_full (fifo_full),
.bus_cycle (m_axi_cyc || m_axi_bresp_cnt != 0),
.xfr_complete (!data_busy),
.crc_error (!data_crc_ok),
.bus_error (m_bus_error),
.int_status (data_int_status),
.int_status_rst (data_int_rst)
);
sd_data_serial_host sd_data_serial_host0(
.clock (clock),
.clock_posedge (clock_posedge),
.clock_data_in (clock_data_in),
.reset (reset | ctrl_rst),
.data_in (fifo_dout),
.rd (tx_fifo_re),
.data_out (data_in_rx_fifo),
.we (rx_fifo_we),
.dat_oe (sd_dat_oe),
.dat_o (sd_dat_o),
.dat_i (sd_dat_i),
.blksize (block_size_reg),
.bus_4bit (controller_setting_reg[0]),
.blkcnt (block_count_reg),
.start ({d_read, d_write}),
.byte_alignment (dma_addr_reg[1:0]),
.sd_data_busy (sd_data_busy),
.busy (data_busy),
.crc_ok (data_crc_ok)
);
assign interrupt =
|(cmd_int_status_reg & cmd_int_enable_reg) ||
|(data_int_status_reg & data_int_enable_reg) ||
(sd_insert_int & sd_insert_ie) ||
(sd_remove_int & sd_remove_ie);
endmodule

502
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@ -0,0 +1,502 @@
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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013-2022 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from https://www.gnu.org/licenses/ ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
module sd_cmd_master(
input clock,
input clock_posedge,
input reset,
input start,
input int_status_rst,
output [1:0] setting,
output reg start_xfr,
output reg go_idle,
output reg [39:0] cmd,
input [119:0] response,
input crc_error,
input index_ok,
input finish,
input busy, // direct signal from data sd data input (data[0])
//input card_detect,
input [31:0] argument,
input [`CMD_REG_SIZE-1:0] command,
input [`CMD_TIMEOUT_W-1:0] timeout,
output [`INT_CMD_SIZE-1:0] int_status,
output reg [31:0] response_0,
output reg [31:0] response_1,
output reg [31:0] response_2,
output reg [31:0] response_3
);
reg expect_response;
reg long_response;
reg [`INT_CMD_SIZE-1:0] int_status_reg;
reg [`CMD_TIMEOUT_W-1:0] watchdog;
reg watchdog_enable;
reg [2:0] state;
parameter IDLE = 3'b001;
parameter EXECUTE = 3'b010;
parameter BUSY_CHECK = 3'b100;
assign setting[1:0] = {long_response, expect_response};
assign int_status = state == IDLE ? int_status_reg : 5'h0;
always @(posedge clock) begin
if (reset) begin
response_0 <= 0;
response_1 <= 0;
response_2 <= 0;
response_3 <= 0;
int_status_reg <= 0;
expect_response <= 0;
long_response <= 0;
cmd <= 0;
start_xfr <= 0;
watchdog <= 0;
watchdog_enable <= 0;
go_idle <= 0;
state <= IDLE;
end else if (clock_posedge) begin
case (state)
IDLE: begin
go_idle <= 0;
if (command[`CMD_RESPONSE_CHECK] == 2'b10 || command[`CMD_RESPONSE_CHECK] == 2'b11) begin
expect_response <= 1;
long_response <= 1;
end else if (command[`CMD_RESPONSE_CHECK] == 2'b01) begin
expect_response <= 1;
long_response <= 0;
end else begin
expect_response <= 0;
long_response <= 0;
end
cmd[39:38] <= 2'b01;
cmd[37:32] <= command[`CMD_INDEX];
cmd[31:0] <= argument;
watchdog <= 0;
watchdog_enable <= timeout != 0;
if (start) begin
start_xfr <= 1;
int_status_reg <= 0;
state <= EXECUTE;
end
end
EXECUTE: begin
start_xfr <= 0;
if (watchdog_enable && watchdog >= timeout) begin
int_status_reg[`INT_CMD_CTE] <= 1;
int_status_reg[`INT_CMD_EI] <= 1;
go_idle <= 1;
state <= IDLE;
end else if (finish) begin
if (command[`CMD_CRC_CHECK] && crc_error) begin
int_status_reg[`INT_CMD_CCRCE] <= 1;
int_status_reg[`INT_CMD_EI] <= 1;
end
if (command[`CMD_IDX_CHECK] && !index_ok) begin
int_status_reg[`INT_CMD_CIE] <= 1;
int_status_reg[`INT_CMD_EI] <= 1;
end
int_status_reg[`INT_CMD_CC] <= 1;
if (expect_response) begin
response_0 <= response[119:88];
response_1 <= response[87:56];
response_2 <= response[55:24];
response_3 <= {response[23:0], 8'h00};
end
if (command[`CMD_BUSY_CHECK]) state <= BUSY_CHECK;
else state <= IDLE;
end else if (watchdog_enable) begin
watchdog <= watchdog + 1;
end
end
BUSY_CHECK: begin
if (!busy) state <= IDLE;
end
endcase
if (int_status_rst)
int_status_reg <= 0;
end
end
endmodule

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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013-2022 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from https://www.gnu.org/licenses/ ////
//// ////
//////////////////////////////////////////////////////////////////////
module sd_cmd_serial_host (
//---------------Input ports---------------
input clock,
input clock_posedge,
input clock_data_in,
input reset,
input [1:0] setting,
input [39:0] cmd,
input start,
input cmd_i,
//---------------Output ports---------------
output reg [119:0] response,
output reg finish,
output reg crc_ok,
output reg index_ok,
output reg cmd_oe,
output reg cmd_o
);
//-------------Internal Constant-------------
parameter INIT_DELAY = 4;
parameter BITS_TO_SEND = 48;
parameter CMD_SIZE = 40;
parameter RESP_SIZE = 128;
//---------------Internal variable-----------
reg cmd_dat_reg;
integer resp_len;
reg with_response;
reg [CMD_SIZE-1:0] cmd_buff;
reg [RESP_SIZE-1:0] resp_buff;
integer resp_idx;
//CRC
reg crc_rst;
reg [6:0]crc_in;
wire [6:0] crc_val;
reg crc_enable;
reg crc_bit;
reg crc_match;
//-Internal Counterns
integer counter;
//-State Machine
parameter
STATE_SIZE = 8,
INIT = 8'b00000001,
IDLE = 8'b00000010,
SETUP_CRC = 8'b00000100,
WRITE = 8'b00001000,
READ_WAIT = 8'b00010000,
READ = 8'b00100000,
FINISH_WR = 8'b01000000,
FINISH_WO = 8'b10000000;
reg [STATE_SIZE-1:0] state;
//Misc
`define cmd_idx (CMD_SIZE-1-counter)
//sd cmd input pad register
always @(posedge clock) begin
if (clock_data_in) cmd_dat_reg <= cmd_i;
end
//------------------------------------------
sd_crc_7 CRC_7(
crc_bit,
crc_enable & clock_posedge,
clock,
crc_rst,
crc_val);
//------------------------------------------
always @(posedge clock) begin
if (reset) begin
resp_len <= 0;
with_response <= 0;
cmd_buff <= 0;
crc_enable <= 0;
resp_idx <= 0;
cmd_oe <= 1;
cmd_o <= 1;
resp_buff <= 0;
finish <= 0;
crc_rst <= 1;
crc_bit <= 0;
crc_in <= 0;
response <= 0;
index_ok <= 0;
crc_ok <= 0;
crc_match <= 0;
counter <= 0;
state <= INIT;
end else if (clock_posedge) begin
case (state)
INIT: begin
counter <= counter+1;
// Pull cmd line up
cmd_oe <= 1;
cmd_o <= 1;
if (counter >= INIT_DELAY) state <= IDLE;
end
IDLE: begin
cmd_oe <= 0;
counter <= 0;
crc_rst <= 1;
crc_enable <= 0;
response <= 0;
resp_idx <= 0;
crc_ok <= 0;
index_ok <= 0;
finish <= 0;
if (start) begin
resp_len <= setting[1] ? 127 : 39;
with_response <= setting[0];
cmd_buff <= cmd;
state <= SETUP_CRC;
end
end
SETUP_CRC: begin
crc_rst <= 0;
crc_enable <= 1;
crc_bit <= cmd_buff[`cmd_idx];
state <= WRITE;
end
WRITE: begin
if (counter < BITS_TO_SEND-8) begin // 1->40 CMD, (41 >= CNT && CNT <=47) CRC, 48 stop_bit
cmd_oe <= 1;
cmd_o <= cmd_buff[`cmd_idx];
if (counter < BITS_TO_SEND-9) begin //1 step ahead
crc_bit <= cmd_buff[`cmd_idx-1];
end else begin
crc_enable <= 0;
end
end else if (counter < BITS_TO_SEND-1) begin
cmd_oe <= 1;
crc_enable <= 0;
cmd_o <= crc_val[BITS_TO_SEND-counter-2];
end else if (counter == BITS_TO_SEND-1) begin
cmd_oe <= 1;
cmd_o <= 1'b1;
end else begin
cmd_oe <= 0;
cmd_o <= 1'b1;
end
counter <= counter + 1;
if (counter >= BITS_TO_SEND && with_response) state <= READ_WAIT;
else if (counter >= BITS_TO_SEND) state <= FINISH_WO;
end
READ_WAIT: begin
crc_enable <= 0;
crc_rst <= 1;
counter <= 1;
cmd_oe <= 0;
resp_buff[RESP_SIZE-1] <= cmd_dat_reg;
if (!cmd_dat_reg) state <= READ;
end
FINISH_WO: begin
finish <= 1;
crc_enable <= 0;
crc_rst <= 1;
counter <= 0;
cmd_oe <= 0;
state <= IDLE;
end
READ: begin
crc_rst <= 0;
crc_enable <= (resp_len != RESP_SIZE-1 || counter > 7);
cmd_oe <= 0;
if (counter <= resp_len) begin
if (counter < 8) //1+1+6 (S,T,Index)
resp_buff[RESP_SIZE-1-counter] <= cmd_dat_reg;
else begin
resp_idx <= resp_idx + 1;
resp_buff[RESP_SIZE-9-resp_idx] <= cmd_dat_reg;
end
crc_bit <= cmd_dat_reg;
end else if (counter-resp_len <= 7) begin
crc_in[(resp_len+7)-(counter)] <= cmd_dat_reg;
crc_enable <= 0;
end else begin
crc_enable <= 0;
crc_match <= crc_in == crc_val;
end
counter <= counter + 1;
if (counter >= resp_len+8) state <= FINISH_WR;
end
FINISH_WR: begin
index_ok <= cmd_buff[37:32] == resp_buff[125:120];
crc_ok <= crc_match;
finish <= 1;
crc_enable <= 0;
crc_rst <= 1;
counter <= 0;
cmd_oe <= 0;
response <= resp_buff[119:0];
state <= IDLE;
end
default:
state <= INIT;
endcase
end
end
endmodule
module sd_crc_7(
input BITVAL, // Next input bit
input ENABLE, // Enable calculation
input BITSTRB, // Current bit valid (Clock)
input CLEAR, // Init CRC value
output reg [6:0] CRC // Current output CRC value
);
wire inv;
assign inv = BITVAL ^ CRC[6];
always @(posedge BITSTRB or posedge CLEAR) begin
if (CLEAR) begin
CRC <= 0;
end else if (ENABLE == 1) begin
CRC[6] <= CRC[5];
CRC[5] <= CRC[4];
CRC[4] <= CRC[3];
CRC[3] <= CRC[2] ^ inv;
CRC[2] <= CRC[1];
CRC[1] <= CRC[0];
CRC[0] <= inv;
end
end
endmodule

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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013-2022 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from https://www.gnu.org/licenses/ ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
module sd_data_master (
input clock,
input clock_posedge,
input reset,
input start_tx,
input start_rx,
input [`DATA_TIMEOUT_W-1:0] timeout,
// Output to SD-Host Reg
output reg d_write,
output reg d_read,
// To fifo filler
output reg en_tx_fifo,
output reg en_rx_fifo,
input fifo_empty,
input fifo_ready,
input fifo_full,
input bus_cycle,
// SD-DATA_Host
input xfr_complete,
input crc_error,
input bus_error,
// status output
output reg [`INT_DATA_SIZE-1:0] int_status,
input int_status_rst
);
reg [3:0] state;
localparam IDLE = 4'b0001;
localparam START_TX_FIFO = 4'b0010;
localparam START_RX_FIFO = 4'b0100;
localparam DATA_TRANSFER = 4'b1000;
reg [`DATA_TIMEOUT_W-1:0] watchdog;
reg watchdog_enable;
always @(posedge clock) begin
if (reset) begin
en_tx_fifo <= 0;
en_rx_fifo <= 0;
d_write <= 0;
d_read <= 0;
int_status <= 0;
watchdog <= 0;
watchdog_enable <= 0;
state <= IDLE;
end else if (clock_posedge) begin
case (state)
IDLE: begin
en_tx_fifo <= 0;
en_rx_fifo <= 0;
d_write <= 0;
d_read <= 0;
watchdog <= 0;
watchdog_enable <= timeout != 0;
if (start_tx) state <= START_TX_FIFO;
else if (start_rx) state <= START_RX_FIFO;
end
START_RX_FIFO: begin
en_rx_fifo <= 1;
en_tx_fifo <= 0;
d_read <= 1;
if (!xfr_complete) state <= DATA_TRANSFER;
end
START_TX_FIFO: begin
en_rx_fifo <= 0;
en_tx_fifo <= 1;
if (fifo_ready) begin
d_write <= 1;
if (!xfr_complete) state <= DATA_TRANSFER;
end
end
DATA_TRANSFER: begin
d_read <= 0;
d_write <= 0;
if (en_tx_fifo && fifo_empty) begin
int_status[`INT_DATA_CFE] <= 1;
int_status[`INT_DATA_EI] <= 1;
state <= IDLE;
// stop sd_data_serial_host
d_write <= 1;
d_read <= 1;
end else if (en_rx_fifo && fifo_full) begin
int_status[`INT_DATA_CFE] <= 1;
int_status[`INT_DATA_EI] <= 1;
state <= IDLE;
// stop sd_data_serial_host
d_write <= 1;
d_read <= 1;
end else if (watchdog_enable && watchdog >= timeout) begin
int_status[`INT_DATA_CTE] <= 1;
int_status[`INT_DATA_EI] <= 1;
state <= IDLE;
// stop sd_data_serial_host
d_write <= 1;
d_read <= 1;
end else if (xfr_complete && !bus_cycle && (en_tx_fifo || fifo_empty)) begin
state <= IDLE;
if (crc_error) begin
int_status[`INT_DATA_CCRCE] <= 1;
int_status[`INT_DATA_EI] <= 1;
end
if (bus_error) begin
int_status[`INT_DATA_CBE] <= 1;
int_status[`INT_DATA_EI] <= 1;
end
int_status[`INT_DATA_CC] <= 1;
end else if (watchdog_enable) begin
watchdog <= watchdog + 1;
end
end
endcase
if (int_status_rst)
int_status <= 0;
end
end
endmodule

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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013-2022 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from https://www.gnu.org/licenses/ ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
module sd_data_serial_host(
input clock,
input clock_posedge,
input clock_data_in,
input reset,
// Tx Fifo
input [31:0] data_in,
output reg rd,
// Rx Fifo
output reg [31:0] data_out,
output reg we,
// tristate data
output reg dat_oe,
output reg[3:0] dat_o,
input [3:0] dat_i,
// Controll signals
input [`BLKSIZE_W-1:0] blksize,
input bus_4bit,
input [`BLKCNT_W-1:0] blkcnt,
input [1:0] start,
input [1:0] byte_alignment,
output sd_data_busy,
output busy,
output reg crc_ok
);
reg [3:0] DAT_dat_reg;
reg bus_4bit_reg;
reg crc_en;
reg crc_rst;
wire [15:0] crc_out [3:0];
reg [`BLKSIZE_W+4-1:0] data_cycles;
reg [`BLKSIZE_W+4-1:0] transf_cnt;
reg [3:0] drt_bit;
reg [3:0] drt_reg;
reg [`BLKCNT_W-1:0] blkcnt_reg;
reg [1:0] byte_alignment_reg;
reg [3:0] crc_bit;
reg [3:0] last_din;
reg [4:0] data_index;
reg [6:0] state;
parameter IDLE = 7'b0000001;
parameter WRITE_DAT = 7'b0000010;
parameter WRITE_WAIT = 7'b0000100;
parameter WRITE_DRT = 7'b0001000;
parameter WRITE_BUSY = 7'b0010000;
parameter READ_WAIT = 7'b0100000;
parameter READ_DAT = 7'b1000000;
// sd data input pad register
always @(posedge clock) begin
if (clock_data_in) DAT_dat_reg <= dat_i;
end
genvar i;
generate
for (i=0; i<4; i=i+1) begin: CRC_16_gen
sd_crc_16 CRC_16_i (last_din[i], crc_en & clock_posedge, clock, crc_rst, crc_out[i]);
end
endgenerate
assign busy = (state != IDLE);
assign sd_data_busy = !DAT_dat_reg[0];
always @(posedge clock) begin
if (reset) begin
state <= IDLE;
dat_oe <= 0;
crc_en <= 0;
crc_rst <= 1;
transf_cnt <= 0;
rd <= 0;
last_din <= 0;
crc_bit <= 0;
dat_o <= 4'b1111;
drt_bit <= 0;
drt_reg <= 0;
we <= 0;
data_out <= 0;
crc_ok <= 0;
data_index <= 0;
blkcnt_reg <= 0;
byte_alignment_reg <= 0;
data_cycles <= 0;
bus_4bit_reg <= 0;
end else if (clock_posedge) begin
case (state)
IDLE: begin
dat_oe <= 0;
dat_o <= 4'b1111;
transf_cnt <= 0;
crc_en <= 0;
crc_rst <= 1;
crc_bit <= 15;
we <= 0;
rd <= 0;
data_index <= 0;
blkcnt_reg <= blkcnt;
byte_alignment_reg <= byte_alignment;
data_cycles <= (bus_4bit ? {3'b000, blksize, 1'b0} + 2 : {1'b0, blksize, 3'b000} + 8);
bus_4bit_reg <= bus_4bit;
if (start == 2'b01) state <= WRITE_DAT;
else if (start == 2'b10) state <= READ_WAIT;
end
WRITE_DAT: begin
rd <= 0;
transf_cnt <= transf_cnt + 16'h1;
if (transf_cnt == 0) begin
crc_ok <= 0;
crc_bit <= 15;
end else if (transf_cnt == 1) begin
crc_rst <= 0;
crc_en <= 1;
if (bus_4bit_reg) begin
last_din <= {
data_in[31-(byte_alignment_reg << 3)],
data_in[30-(byte_alignment_reg << 3)],
data_in[29-(byte_alignment_reg << 3)],
data_in[28-(byte_alignment_reg << 3)]
};
end else begin
last_din <= {3'h7, data_in[31-(byte_alignment_reg << 3)]};
end
dat_oe <= 1;
dat_o <= bus_4bit_reg ? 4'h0 : 4'he;
data_index <= bus_4bit_reg ? {2'b00, byte_alignment_reg, 1'b1} : {byte_alignment_reg, 3'b001};
end else if (transf_cnt <= data_cycles+1) begin
if (bus_4bit_reg) begin
last_din <= {
data_in[31-(data_index[2:0]<<2)],
data_in[30-(data_index[2:0]<<2)],
data_in[29-(data_index[2:0]<<2)],
data_in[28-(data_index[2:0]<<2)]
};
if (data_index[2:0] == 3'h6 && transf_cnt <= data_cycles-1) rd <= 1;
end else begin
last_din <= {3'h7, data_in[31-data_index]};
if (data_index == 30) rd <= 1;
end
data_index <= data_index + 5'h1;
dat_o <= last_din;
if (transf_cnt == data_cycles+1) crc_en <= 0;
end else if (transf_cnt <= data_cycles+17) begin
crc_en <= 0;
dat_o[0] <= crc_out[0][crc_bit];
if (bus_4bit_reg)
dat_o[3:1] <= {crc_out[3][crc_bit], crc_out[2][crc_bit], crc_out[1][crc_bit]};
crc_bit <= crc_bit - 1;
end else if (transf_cnt == data_cycles+18) begin
dat_o <= 4'hf;
end else if (transf_cnt == data_cycles+19) begin
dat_oe <= 0;
end else begin
state <= WRITE_WAIT;
end
end
WRITE_WAIT: begin
drt_bit <= 0;
if (!DAT_dat_reg[0]) state <= WRITE_DRT;
end
WRITE_DRT: begin
// See 7.3.3.1 Data Response Token
if (drt_bit <= 3) begin
drt_reg[drt_bit] <= DAT_dat_reg[0];
end else if (drt_bit == 15) begin
crc_ok <= drt_reg[3:0] == 4'b1010;
state <= WRITE_BUSY;
end
drt_bit <= drt_bit + 1;
end
WRITE_BUSY: begin
if (DAT_dat_reg[0]) begin
if (blkcnt_reg != 0 && crc_ok) begin
transf_cnt <= 0;
blkcnt_reg <= blkcnt_reg - 1;
byte_alignment_reg <= byte_alignment_reg + blksize[1:0] + 2'b1;
crc_rst <= 1;
state <= WRITE_DAT;
end else begin
state <= IDLE;
end
end
end
READ_WAIT: begin
dat_oe <= 0;
crc_bit <= 15;
last_din <= 0;
transf_cnt <= 0;
data_index <= bus_4bit_reg ? (byte_alignment_reg << 1) : (byte_alignment_reg << 3);
if (!DAT_dat_reg[0]) begin
crc_rst <= 0;
crc_en <= 1;
state <= READ_DAT;
end
end
READ_DAT: begin
last_din <= DAT_dat_reg;
transf_cnt <= transf_cnt + 16'h1;
if (transf_cnt < data_cycles) begin
if (bus_4bit_reg) begin
we <= (data_index[2:0] == 7 || (transf_cnt == data_cycles-1 && !blkcnt_reg));
data_out[31-(data_index[2:0]<<2)] <= DAT_dat_reg[3];
data_out[30-(data_index[2:0]<<2)] <= DAT_dat_reg[2];
data_out[29-(data_index[2:0]<<2)] <= DAT_dat_reg[1];
data_out[28-(data_index[2:0]<<2)] <= DAT_dat_reg[0];
end else begin
we <= (data_index == 31 || (transf_cnt == data_cycles-1 && !blkcnt_reg));
data_out[31-data_index] <= DAT_dat_reg[0];
end
data_index <= data_index + 5'h1;
crc_ok <= 1;
end else if (transf_cnt == data_cycles) begin
crc_en <= 0;
we <= 0;
end else if (transf_cnt <= data_cycles+16) begin
if (crc_out[0][crc_bit] != last_din[0]) crc_ok <= 0;
if (bus_4bit_reg) begin
if (crc_out[1][crc_bit] != last_din[1]) crc_ok <= 0;
if (crc_out[2][crc_bit] != last_din[2]) crc_ok <= 0;
if (crc_out[3][crc_bit] != last_din[3]) crc_ok <= 0;
end
if (crc_bit == 0) begin
byte_alignment_reg <= byte_alignment_reg + blksize[1:0] + 2'b1;
crc_rst <= 1;
end else begin
crc_bit <= crc_bit - 1;
end
end else if (blkcnt_reg != 0 && crc_ok) begin
blkcnt_reg <= blkcnt_reg - 1;
state <= READ_WAIT;
end else begin
state <= IDLE;
end
end
default:
state <= IDLE;
endcase
if (start == 2'b11) state <= IDLE; // Abort
end
end
endmodule
module sd_crc_16(
input BITVAL, // Next input bit
input ENABLE, // Enable calculation
input BITSTRB, // Current bit valid (Clock)
input CLEAR, // Init CRC value
output reg [15:0] CRC // Current output CRC value
);
assign inv = BITVAL ^ CRC[15];
always @(posedge BITSTRB) begin
if (CLEAR) begin
CRC <= 0;
end else if (ENABLE == 1) begin
CRC[15] <= CRC[14];
CRC[14] <= CRC[13];
CRC[13] <= CRC[12];
CRC[12] <= CRC[11] ^ inv;
CRC[11] <= CRC[10];
CRC[10] <= CRC[9];
CRC[9] <= CRC[8];
CRC[8] <= CRC[7];
CRC[7] <= CRC[6];
CRC[6] <= CRC[5];
CRC[5] <= CRC[4] ^ inv;
CRC[4] <= CRC[3];
CRC[3] <= CRC[2];
CRC[2] <= CRC[1];
CRC[1] <= CRC[0];
CRC[0] <= inv;
end
end
endmodule

91
pipelined/src/uncore/newsdc/sd_defines.h Normal file
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@ -0,0 +1,91 @@
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013-2022 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from https://www.gnu.org/licenses/ ////
//// ////
//////////////////////////////////////////////////////////////////////
// global defines
`define BLKSIZE_W 12
`define BLKCNT_W 16
`define CMD_TIMEOUT_W 25
`define DATA_TIMEOUT_W 28
// cmd module interrupts
`define INT_CMD_SIZE 5
`define INT_CMD_CC 0
`define INT_CMD_EI 1
`define INT_CMD_CTE 2
`define INT_CMD_CCRCE 3
`define INT_CMD_CIE 4
// data module interrupts
`define INT_DATA_SIZE 6
`define INT_DATA_CC 0
`define INT_DATA_EI 1
`define INT_DATA_CTE 2 // Timeout
`define INT_DATA_CCRCE 3 // CRC error
`define INT_DATA_CFE 4 // FIFO error
`define INT_DATA_CBE 5 // Bus error
// command register defines
`define CMD_REG_SIZE 14
`define CMD_RESPONSE_CHECK 1:0
`define CMD_BUSY_CHECK 2
`define CMD_CRC_CHECK 3
`define CMD_IDX_CHECK 4
`define CMD_WITH_DATA 6:5
`define CMD_INDEX 13:8
// register addreses
`define argument 8'h00
`define command 8'h04
`define resp0 8'h08
`define resp1 8'h0c
`define resp2 8'h10
`define resp3 8'h14
`define data_timeout 8'h18
`define controller 8'h1c
`define cmd_timeout 8'h20
`define clock_d 8'h24
`define reset 8'h28
`define voltage 8'h2c
`define capa 8'h30
`define cmd_isr 8'h34
`define cmd_iser 8'h38
`define data_isr 8'h3c
`define data_iser 8'h40
`define blksize 8'h44
`define blkcnt 8'h48
`define card_detect 8'h4c
`define dst_src_addr 8'h60
`define dst_src_addr_high 8'h64
// register contents
`define RESET_BLOCK_SIZE 12'd511
`define RESET_CLOCK_DIV 124

2
pipelined/src/uncore/uncore.sv
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@ -31,6 +31,8 @@
`include "wally-config.vh"
// *** need idiom to map onto cache RAM with byte writes
// *** and use memread signal to reduce power when reads aren't needed
module uncore (
// AHB Bus Interface
input logic HCLK, HRESETn,

112
tests/custom/boot/Makefile Normal file
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@ -0,0 +1,112 @@
CEXT := c
CPPEXT := cpp
AEXT := s
SEXT := S
SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\)
OBJEXT := o
DEPEXT := d
SRCDIR := .
BUILDDIR := OBJ
SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort)
OBJECTS := $(SOURCES:.$(CEXT)=.$(OBJEXT))
OBJECTS := $(OBJECTS:.$(AEXT)=.$(OBJEXT))
OBJECTS := $(OBJECTS:.$(SEXT)=.$(OBJEXT))
OBJECTS := $(OBJECTS:.$(CPPEXT)=.$(OBJEXT))
OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS))
TARGETDIR := bin
TARGET := $(TARGETDIR)/fpga-test-sdc
ROOT := ..
LIBRARY_DIRS :=
LIBRARY_FILES :=
MARCH :=-march=rv64imfdc
MABI :=-mabi=lp64d
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles
LINKER :=linker.x
AFLAGS =$(MARCH) $(MABI) -W
CFLAGS =$(MARCH) $(MABI) -mcmodel=medany -O2
AS=riscv64-unknown-elf-as
CC=riscv64-unknown-elf-gcc
AR=riscv64-unknown-elf-ar
#Default Make
all: directories $(TARGET).memfile
#Remake
remake: clean all
#Make the Directories
directories:
@mkdir -p $(TARGETDIR)
@mkdir -p $(BUILDDIR)
clean:
rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump
#Needed for building additional library projects
ifdef LIBRARY_DIRS
LIBS+=${LIBRARY_DIRS:%=-L%} ${LIBRARY_FILES:%=-l%}
INC+=${LIBRARY_DIRS:%=-I%}
${LIBRARY_DIRS}:
make -C $@ -j 1
.PHONY: $(LIBRARY_DIRS) $(TARGET)
endif
#Pull in dependency info for *existing* .o files
-include $(OBJECTS:.$(OBJEXT)=.$(DEPEXT))
#Link
$(TARGET): $(OBJECTS) $(LIBRARY_DIRS)
$(CC) $(LINK_FLAGS) -g -o $(TARGET) $(OBJECTS) ${LIBS} -T ${LINKER}
#Compile
$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CEXT)
@mkdir -p $(dir $@)
$(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list
@$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CEXT) > $(BUILDDIR)/$*.$(DEPEXT)
@cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp
@sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT)
@sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT)
@rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp
# gcc won't output dependencies for assembly files for some reason
# most asm files don't have dependencies so the echo will work for now.
$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(AEXT)
@mkdir -p $(dir $@)
$(CC) $(CFLAGS) -c -o $@ $< > $(BUILDDIR)/$*.list
@echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT)
$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(SEXT)
@mkdir -p $(dir $@)
$(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list
@echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT)
# C++
$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CPPEXT)
@mkdir -p $(dir $@)
$(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list
@$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CPPEXT) > $(BUILDDIR)/$*.$(DEPEXT)
@cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp
@sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT)
@sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT)
@rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp
# convert to hex
$(TARGET).memfile: $(TARGET)
@echo 'Making object dump file.'
@riscv64-unknown-elf-objdump -D $< > $<.objdump
@echo 'Making memory file'
riscv64-unknown-elf-elf2hex --bit-width 64 --input $^ --output $@
extractFunctionRadix.sh $<.objdump
mkdir -p ../../imperas-riscv-tests/work/rv64BP/
cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/

370
tests/custom/boot/boot.c Normal file
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@ -0,0 +1,370 @@
/* Card type flags (card_type) */
#define CT_MMC 0x01 /* MMC ver 3 */
#define CT_SD1 0x02 /* SD ver 1 */
#define CT_SD2 0x04 /* SD ver 2 */
#define CT_SDC (CT_SD1|CT_SD2) /* SD */
#define CT_BLOCK 0x08 /* Block addressing */
#define CMD0 (0) /* GO_IDLE_STATE */
#define CMD1 (1) /* SEND_OP_COND */
#define CMD2 (2) /* SEND_CID */
#define CMD3 (3) /* RELATIVE_ADDR */
#define CMD4 (4)
#define CMD5 (5) /* SLEEP_WAKE (SDC) */
#define CMD6 (6) /* SWITCH_FUNC */
#define CMD7 (7) /* SELECT */
#define CMD8 (8) /* SEND_IF_COND */
#define CMD9 (9) /* SEND_CSD */
#define CMD10 (10) /* SEND_CID */
#define CMD11 (11)
#define CMD12 (12) /* STOP_TRANSMISSION */
#define CMD13 (13)
#define CMD15 (15)
#define CMD16 (16) /* SET_BLOCKLEN */
#define CMD17 (17) /* READ_SINGLE_BLOCK */
#define CMD18 (18) /* READ_MULTIPLE_BLOCK */
#define CMD19 (19)
#define CMD20 (20)
#define CMD23 (23)
#define CMD24 (24)
#define CMD25 (25)
#define CMD27 (27)
#define CMD28 (28)
#define CMD29 (29)
#define CMD30 (30)
#define CMD32 (32)
#define CMD33 (33)
#define CMD38 (38)
#define CMD42 (42)
#define CMD55 (55) /* APP_CMD */
#define CMD56 (56)
#define ACMD6 (0x80+6) /* define the data bus width */
#define ACMD41 (0x80+41) /* SEND_OP_COND (ACMD) */
// Capability bits
#define SDC_CAPABILITY_SD_4BIT 0x0001
#define SDC_CAPABILITY_SD_RESET 0x0002
#define SDC_CAPABILITY_ADDR 0xff00
// Control bits
#define SDC_CONTROL_SD_4BIT 0x0001
#define SDC_CONTROL_SD_RESET 0x0002
// Card detect bits
#define SDC_CARD_INSERT_INT_EN 0x0001
#define SDC_CARD_INSERT_INT_REQ 0x0002
#define SDC_CARD_REMOVE_INT_EN 0x0004
#define SDC_CARD_REMOVE_INT_REQ 0x0008
// Command status bits
#define SDC_CMD_INT_STATUS_CC 0x0001 // Command complete
#define SDC_CMD_INT_STATUS_EI 0x0002 // Any error
#define SDC_CMD_INT_STATUS_CTE 0x0004 // Timeout
#define SDC_CMD_INT_STATUS_CCRC 0x0008 // CRC error
#define SDC_CMD_INT_STATUS_CIE 0x0010 // Command code check error
// Data status bits
#define SDC_DAT_INT_STATUS_TRS 0x0001 // Transfer complete
#define SDC_DAT_INT_STATUS_ERR 0x0002 // Any error
#define SDC_DAT_INT_STATUS_CTE 0x0004 // Timeout
#define SDC_DAT_INT_STATUS_CRC 0x0008 // CRC error
#define SDC_DAT_INT_STATUS_CFE 0x0010 // Data FIFO underrun or overrun
#define ERR_EOF 30
#define ERR_NOT_ELF 31
#define ERR_ELF_BITS 32
#define ERR_ELF_ENDIANNESS 33
#define ERR_CMD_CRC 34
#define ERR_CMD_CHECK 35
#define ERR_DATA_CRC 36
#define ERR_DATA_FIFO 37
#define ERR_BUF_ALIGNMENT 38
struct sdc_regs {
volatile uint32_t argument;
volatile uint32_t command;
volatile uint32_t response1;
volatile uint32_t response2;
volatile uint32_t response3;
volatile uint32_t response4;
volatile uint32_t data_timeout;
volatile uint32_t control;
volatile uint32_t cmd_timeout;
volatile uint32_t clock_divider;
volatile uint32_t software_reset;
volatile uint32_t power_control;
volatile uint32_t capability;
volatile uint32_t cmd_int_status;
volatile uint32_t cmd_int_enable;
volatile uint32_t dat_int_status;
volatile uint32_t dat_int_enable;
volatile uint32_t block_size;
volatile uint32_t block_count;
volatile uint32_t card_detect;
volatile uint32_t res_50;
volatile uint32_t res_54;
volatile uint32_t res_58;
volatile uint32_t res_5c;
volatile uint64_t dma_addres;
};
static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013100;
static int errno __attribute__((section(".bss")));
static DSTATUS drv_status __attribute__((section(".bss")));
static BYTE card_type __attribute__((section(".bss")));
static uint32_t response[4] __attribute__((section(".bss")));
static FATFS fatfs __attribute__((section(".bss")));
static int alt_mem __attribute__((section(".bss")));
static FIL fd __attribute__((section(".bss")));
extern unsigned char _fbss[];
extern unsigned char _ebss[];
static const char * errno_to_str(void) {
switch (errno) {
case FR_OK: return "No error";
case FR_DISK_ERR: return "Disk I/O error";
case FR_INT_ERR: return "Assertion failed";
case FR_NOT_READY: return "Disk not ready";
case FR_NO_FILE: return "File not found";
case FR_NO_PATH: return "Path not found";
case FR_INVALID_NAME: return "Invalid path";
case FR_DENIED: return "Access denied";
case FR_EXIST: return "Already exist";
case FR_INVALID_OBJECT: return "The FS object is invalid";
case FR_WRITE_PROTECTED: return "The drive is write protected";
case FR_INVALID_DRIVE: return "The drive number is invalid";
case FR_NOT_ENABLED: return "The volume has no work area";
case FR_NO_FILESYSTEM: return "Not a valid FAT volume";
case FR_MKFS_ABORTED: return "The f_mkfs() aborted";
case FR_TIMEOUT: return "Timeout";
case FR_LOCKED: return "Locked";
case FR_NOT_ENOUGH_CORE: return "Not enough memory";
case FR_TOO_MANY_OPEN_FILES: return "Too many open files";
case ERR_EOF: return "Unexpected EOF";
case ERR_NOT_ELF: return "Not an ELF file";
case ERR_ELF_BITS: return "Wrong ELF word size";
case ERR_ELF_ENDIANNESS: return "Wrong ELF endianness";
case ERR_CMD_CRC: return "Command CRC error";
case ERR_CMD_CHECK: return "Command code check error";
case ERR_DATA_CRC: return "Data CRC error";
case ERR_DATA_FIFO: return "Data FIFO error";
case ERR_BUF_ALIGNMENT: return "Bad buffer alignment";
}
return "Unknown error code";
}
static void usleep(unsigned us) {
uintptr_t cycles0;
uintptr_t cycles1;
asm volatile ("csrr %0, 0xB00" : "=r" (cycles0));
for (;;) {
asm volatile ("csrr %0, 0xB00" : "=r" (cycles1));
if (cycles1 - cycles0 >= us * 100) break;
}
}
static int sdc_cmd_finish(unsigned cmd) {
while (1) {
unsigned status = regs->cmd_int_status;
if (status) {
// clear interrupts
regs->cmd_int_status = 0;
while (regs->software_reset != 0) {}
if (status == SDC_CMD_INT_STATUS_CC) {
// get response
response[0] = regs->response1;
response[1] = regs->response2;
response[2] = regs->response3;
response[3] = regs->response4;
return 0;
}
errno = FR_DISK_ERR;
if (status & SDC_CMD_INT_STATUS_CTE) errno = FR_TIMEOUT;
if (status & SDC_CMD_INT_STATUS_CCRC) errno = ERR_CMD_CRC;
if (status & SDC_CMD_INT_STATUS_CIE) errno = ERR_CMD_CHECK;
break;
}
}
return -1;
}
static int sdc_data_finish(void) {
int status;
while ((status = regs->dat_int_status) == 0) {}
regs->dat_int_status = 0;
while (regs->software_reset != 0) {}
if (status == SDC_DAT_INT_STATUS_TRS) return 0;
errno = FR_DISK_ERR;
if (status & SDC_DAT_INT_STATUS_CTE) errno = FR_TIMEOUT;
if (status & SDC_DAT_INT_STATUS_CRC) errno = ERR_DATA_CRC;
if (status & SDC_DAT_INT_STATUS_CFE) errno = ERR_DATA_FIFO;
return -1;
}
static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks) {
unsigned command = (cmd & 0x3f) << 8;
switch (cmd) {
case CMD0:
case CMD4:
case CMD15:
// No responce
break;
case CMD11:
case CMD13:
case CMD16:
case CMD17:
case CMD18:
case CMD19:
case CMD23:
case CMD24:
case CMD25:
case CMD27:
case CMD30:
case CMD32:
case CMD33:
case CMD42:
case CMD55:
case CMD56:
case ACMD6:
// R1
command |= 1; // 48 bits
command |= 1 << 3; // resp CRC
command |= 1 << 4; // resp OPCODE
break;
case CMD7:
case CMD12:
case CMD20:
case CMD28:
case CMD29:
case CMD38:
// R1b
command |= 1; // 48 bits
command |= 1 << 2; // busy
command |= 1 << 3; // resp CRC
command |= 1 << 4; // resp OPCODE
break;
case CMD2:
case CMD9:
case CMD10:
// R2
command |= 2; // 136 bits
command |= 1 << 3; // resp CRC
break;
case ACMD41:
// R3
command |= 1; // 48 bits
break;
case CMD3:
// R6
command |= 1; // 48 bits
command |= 1 << 2; // busy
command |= 1 << 3; // resp CRC
command |= 1 << 4; // resp OPCODE
break;
case CMD8:
// R7
command |= 1; // 48 bits
command |= 1 << 3; // resp CRC
command |= 1 << 4; // resp OPCODE
break;
}
if (blocks) {
command |= 1 << 5;
if ((intptr_t)buf & 3) {
errno = ERR_BUF_ALIGNMENT;
return -1;
}
regs->dma_addres = (uint64_t)(intptr_t)buf;
regs->block_size = 511;
regs->block_count = blocks - 1;
regs->data_timeout = 0xFFFFFF;
}
regs->command = command;
regs->cmd_timeout = 0xFFFFF;
regs->argument = arg;
if (sdc_cmd_finish(cmd) < 0) return -1;
if (blocks) return sdc_data_finish();
return 0;
}
#define send_cmd(cmd, arg) send_data_cmd(cmd, arg, NULL, 0)
static int ini_sd(void) {
unsigned rca;
/* Reset controller */
regs->software_reset = 1;
while ((regs->software_reset & 1) == 0) {}
regs->clock_divider = 0x7c;
regs->software_reset = 0;
while (regs->software_reset) {}
usleep(5000);
card_type = 0;
drv_status = STA_NOINIT;
if (regs->capability & SDC_CAPABILITY_SD_RESET) {
/* Power cycle SD card */
regs->control |= SDC_CONTROL_SD_RESET;
usleep(1000000);
regs->control &= ~SDC_CONTROL_SD_RESET;
usleep(100000);
}
/* Enter Idle state */
send_cmd(CMD0, 0);
card_type = CT_SD1;
if (send_cmd(CMD8, 0x1AA) == 0) {
if ((response[0] & 0xfff) != 0x1AA) {
errno = ERR_CMD_CHECK;
return -1;
}
card_type = CT_SD2;
}
/* Wait for leaving idle state (ACMD41 with HCS bit) */
while (1) {
/* ACMD41, Set Operating Conditions: Host High Capacity & 3.3V */
if (send_cmd(CMD55, 0) < 0 || send_cmd(ACMD41, 0x40300000) < 0) return -1;
if (response[0] & (1 << 31)) {
if (response[0] & (1 << 30)) card_type |= CT_BLOCK;
break;
}
}
/* Enter Identification state */
if (send_cmd(CMD2, 0) < 0) return -1;
/* Get RCA (Relative Card Address) */
rca = 0x1234;
if (send_cmd(CMD3, rca << 16) < 0) return -1;
rca = response[0] >> 16;
/* Select card */
if (send_cmd(CMD7, rca << 16) < 0) return -1;
/* Clock 25MHz */
regs->clock_divider = 3;
usleep(10000);
/* Bus width 1-bit */
regs->control = 0;
if (send_cmd(CMD55, rca << 16) < 0 || send_cmd(ACMD6, 0) < 0) return -1;
/* Set R/W block length to 512 */
if (send_cmd(CMD16, 512) < 0) return -1;
drv_status &= ~STA_NOINIT;
return 0;
}