mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-23 13:27:16 -04:00
Merge branch 'main' of github.com:openhwgroup/cvw
This commit is contained in:
Rose Thompson
Rose
commit
faffecf891
8 changed files with 155 additions and 92 deletions
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@ -136,8 +136,8 @@ set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {
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set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCWP}]
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set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
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set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}]
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set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
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set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}]
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set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}]
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set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}]
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@ -158,54 +158,54 @@ set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc
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# ddr3
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0]
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set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]
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set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n
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set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n
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set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1]]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0]]
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set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]]
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set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0]]
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set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]]
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@ -37,12 +37,29 @@
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#include "riscv.h"
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#include "fail.h"
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// Maximum SD card clock frequency is either 20MHz or half of the
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// system clock
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/*
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PSEUDOCODE:
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transmit 8 dummy bytes
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wait for receive fifo to get a byte.
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- as soon as a byte is in the receive fifo
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- process the byte and increment a byte counter.
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when 8 bytes are transferred
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*/
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int disk_read(BYTE * buf, LBA_t sector, UINT count) {
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uint64_t r;
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UINT i;
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UINT i, j;
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volatile uint8_t *p = buf;
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UINT modulus = count/50;
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// Quarter of the Systemclock, divided by the number of bits in a block
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// equals the number of blocks per second transferred.
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UINT modulus = SDCCLOCK/(8*512);
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uint8_t crc = 0;
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crc = crc7(crc, 0x40 | SD_CMD_READ_BLOCK_MULTIPLE);
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@ -72,22 +89,30 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) {
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// Wait for data token
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while((r = spi_dummy()) != SD_DATA_TOKEN);
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// println_with_byte("Received data token: 0x", r & 0xff);
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// println_with_dec("Block ", i);
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// Read block into memory.
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/* for (int j = 0; j < 64; j++) { */
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/* *buf = sd_read64(&crc); */
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/* println_with_addr("0x", *buf); */
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/* buf = buf + 64; */
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/* } */
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crc = 0;
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n = 512;
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/* n = 512; */
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/* do { */
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/* uint8_t x = spi_dummy(); */
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/* *p++ = x; */
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/* crc = crc16(crc, x); */
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/* } while (--n > 0); */
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n = 512/8;
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do {
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uint8_t x = spi_dummy();
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*p++ = x;
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crc = crc16(crc, x);
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} while (--n > 0);
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// Send 8 dummy bytes (fifo should be empty)
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for (j = 0; j < 8; j++) {
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spi_sendbyte(0xff);
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}
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// Reset counter. Process bytes AS THEY COME IN.
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for (j = 0; j < 8; j++) {
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while (!(read_reg(SPI_IP) & 2)) {}
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uint8_t x = spi_readbyte();
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*p++ = x;
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crc = crc16(crc, x);
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}
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} while(--n > 0);
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// Read CRC16 and check
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crc_exp = ((uint16_t)spi_dummy() << 8);
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@ -116,8 +141,6 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) {
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print_uart_dec(count);
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print_uart("/");
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print_uart_dec(count);
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// write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_AUTO);
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//spi_txrx(0xff);
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print_uart("\r\n");
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return 0;
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}
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@ -140,7 +163,7 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) {
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/* print_uart("\r\n"); */
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// Intialize the SD card
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init_sd(SYSTEMCLOCK, 5000000);
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init_sd(SYSTEMCLOCK, SDCCLOCK);
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ret = gpt_load_partitions();
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}
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@ -63,5 +63,14 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count);
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#define SYSTEMCLOCK 20000000
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// TODO: This line needs to change back to 20MHz when we fix the
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// timing problems.
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#define MAXSDCCLOCK 5000000
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// Maximum SDC speed is either the system clock divided by 2 (because
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// of the SPI peripheral clock division) or the maximum speed an SD
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// card can be pushed to.
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#define SDCCLOCK (SYSTEMCLOCK/2 > MAXSDCCLOCK ? MAXSDCCLOCK : SYSTEMCLOCK/2)
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#endif // WALLYBOOT
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@ -148,8 +148,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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// APB access
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assign Entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses
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assign Memwrite = PWRITE & PENABLE & PSEL; // Only write in access phase
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// JACOB: This shouldn't behave this way
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assign PREADY = TransmitInactive; // Tie PREADY to transmission for hardware interlock
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assign PREADY = Entry == SPI_TXDATA | Entry == SPI_RXDATA | TransmitInactive; // Tie PREADY to transmission for hardware interlock
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// Account for subword read/write circuitry
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// -- Note SPI registers are 32 bits no matter what; access them with LW SW.
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@ -187,12 +186,16 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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SPI_CSMODE: ChipSelectMode <= Din[1:0];
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SPI_DELAY0: Delay0 <= {Din[23:16], Din[7:0]};
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SPI_DELAY1: Delay1 <= {Din[23:16], Din[7:0]};
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SPI_FMT: Format <= {Din[19:16], Din[2]};
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SPI_TXDATA: if (~TransmitFIFOWriteFull) TransmitData[7:0] <= Din[7:0];
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SPI_FMT: Format <= {Din[19:16], Din[2]};
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SPI_TXMARK: TransmitWatermark <= Din[2:0];
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SPI_RXMARK: ReceiveWatermark <= Din[2:0];
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SPI_IE: InterruptEnable <= Din[1:0];
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endcase
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if (Memwrite)
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case(Entry)
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SPI_TXDATA: if (~TransmitFIFOWriteFull) TransmitData[7:0] <= Din[7:0];
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endcase
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/* verilator lint_off CASEINCOMPLETE */
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// According to FU540 spec: Once interrupt is pending, it will remain set until number
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@ -268,11 +271,11 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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always_ff @(posedge PCLK)
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if (~PRESETn) TransmitFIFOWriteIncrement <= 1'b0;
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else TransmitFIFOWriteIncrement <= (Memwrite & (Entry == 8'h48) & ~TransmitFIFOWriteFull & TransmitInactive);
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else TransmitFIFOWriteIncrement <= (Memwrite & (Entry == SPI_TXDATA) & ~TransmitFIFOWriteFull);
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always_ff @(posedge PCLK)
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if (~PRESETn) ReceiveFIFOReadIncrement <= 1'b0;
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else ReceiveFIFOReadIncrement <= ((Entry == 8'h4C) & ~ReceiveFIFOReadEmpty & PSEL & ~ReceiveFIFOReadIncrement);
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else ReceiveFIFOReadIncrement <= ((Entry == SPI_RXDATA) & ~ReceiveFIFOReadEmpty & PSEL & ~ReceiveFIFOReadIncrement);
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// Tx/Rx FIFOs
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spi_fifo #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn, TransmitFIFOWriteIncrement, TransmitShiftEmpty, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0],
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@ -300,7 +303,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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always_ff @(posedge PCLK)
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if (~PRESETn) begin
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state <= CS_INACTIVE;
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FrameCount <= 4'b0;
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FrameCount <= 4'b0;
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SPICLK <= SckMode[1];
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end else if (SCLKenable) begin
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/* verilator lint_off CASEINCOMPLETE */
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case (state)
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@ -311,21 +315,32 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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InterCSCount <= 9'b10;
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InterXFRCount <= 9'b1;
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if ((~TransmitFIFOReadEmpty | ~TransmitShiftEmpty) & ((|(Delay0[7:0])) | ~SckMode[0])) state <= DELAY_0;
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else if ((~TransmitFIFOReadEmpty | ~TransmitShiftEmpty)) state <= ACTIVE_0;
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else if ((~TransmitFIFOReadEmpty | ~TransmitShiftEmpty)) begin
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state <= ACTIVE_0;
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SPICLK <= ~SckMode[1];
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end else SPICLK <= SckMode[1];
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end
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DELAY_0: begin
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CS_SCKCount <= CS_SCKCount + 9'b1;
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if (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1)) state <= ACTIVE_0;
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if (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1)) begin
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state <= ACTIVE_0;
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SPICLK <= ~SckMode[1];
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end
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end
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ACTIVE_0: begin
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FrameCount <= FrameCount + 4'b1;
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SPICLK <= SckMode[1];
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state <= ACTIVE_1;
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end
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ACTIVE_1: begin
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InterXFRCount <= 9'b1;
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if (FrameCount < Format[4:1]) state <= ACTIVE_0;
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if (FrameCount < Format[4:1]) begin
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state <= ACTIVE_0;
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SPICLK <= ~SckMode[1];
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end
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else if ((ChipSelectMode[1:0] == 2'b10) & ~|(Delay1[15:8]) & (~TransmitFIFOReadEmpty)) begin
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state <= ACTIVE_0;
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SPICLK <= ~SckMode[1];
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CS_SCKCount <= 9'b1;
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SCK_CSCount <= 9'b10;
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FrameCount <= 4'b0;
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@ -341,6 +356,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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end
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INTER_CS: begin
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InterCSCount <= InterCSCount + 9'b1;
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SPICLK <= SckMode[1];
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if (InterCSCount >= ({Delay1[7:0],1'b0})) state <= CS_INACTIVE;
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end
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INTER_XFR: begin
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@ -349,8 +365,11 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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FrameCount <= 4'b0;
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InterCSCount <= 9'b10;
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InterXFRCount <= InterXFRCount + 9'b1;
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if ((InterXFRCount >= ({Delay1[15:8], 1'b0})) & ~TransmitFIFOReadEmptyDelay) state <= ACTIVE_0;
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||||
else if (~|ChipSelectMode[1:0]) state <= CS_INACTIVE;
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if ((InterXFRCount >= ({Delay1[15:8], 1'b0})) & ~TransmitFIFOReadEmptyDelay) begin
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||||
state <= ACTIVE_0;
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||||
SPICLK <= ~SckMode[1];
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||||
end else if (~|ChipSelectMode[1:0]) state <= CS_INACTIVE;
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||||
else SPICLK <= SckMode[1];
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||||
end
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||||
endcase
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||||
/* verilator lint_off CASEINCOMPLETE */
|
||||
|
|
@ -360,32 +379,28 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
|||
|
||||
assign DelayMode = SckMode[0] ? (state == DELAY_1) : (state == ACTIVE_1 & ReceiveShiftFull);
|
||||
assign ChipSelectInternal = (state == CS_INACTIVE | state == INTER_CS | DelayMode & ~|(Delay0[15:8])) ? ChipSelectDef : ~ChipSelectDef;
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||||
assign SPICLK = (state == ACTIVE_0) ? ~SckMode[1] : SckMode[1];
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||||
assign Active = (state == ACTIVE_0 | state == ACTIVE_1);
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||||
assign SampleEdge = SckMode[0] ? (state == ACTIVE_1) : (state == ACTIVE_0);
|
||||
assign ZeroDelayHoldMode = ((ChipSelectMode == 2'b10) & (~|(Delay1[7:4])));
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||||
assign TransmitInactive = ((state == INTER_CS) | (state == CS_INACTIVE) | (state == INTER_XFR) | (ReceiveShiftFullDelayPCLK & ZeroDelayHoldMode));
|
||||
assign TransmitInactive = ((state == INTER_CS) | (state == CS_INACTIVE) | (state == INTER_XFR) | (ReceiveShiftFullDelayPCLK & ZeroDelayHoldMode) | ((state == ACTIVE_1) & ((ChipSelectMode[1:0] == 2'b10) & ~|(Delay1[15:8]) & (~TransmitFIFOReadEmpty) & (FrameCount == Format[4:1]))));
|
||||
assign Active0 = (state == ACTIVE_0);
|
||||
|
||||
// Signal tracks which edge of sck to shift data
|
||||
// Jacob: We need to confirm that this represents the actual polarity and phase options for sampling.
|
||||
// The first option now samples on the leading edge and shifts on the falling edge like it's supposed to.
|
||||
// We need to confirm the validity of the other options.
|
||||
always_comb
|
||||
case(SckMode[1:0])
|
||||
2'b00: ShiftEdge = SPICLK & SCLKenable;
|
||||
2'b01: ShiftEdge = (SPICLK & |(FrameCount) & SCLKenable); // Probably wrong
|
||||
2'b10: ShiftEdge = ~SPICLK & SCLKenable; // Probably wrong
|
||||
2'b11: ShiftEdge = (~SPICLK & |(FrameCount) & SCLKenable); // Probably wrong
|
||||
2'b01: ShiftEdge = (~SPICLK & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive);
|
||||
2'b10: ShiftEdge = ~SPICLK & SCLKenable;
|
||||
2'b11: ShiftEdge = (SPICLK & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive);
|
||||
default: ShiftEdge = SPICLK & SCLKenable;
|
||||
endcase
|
||||
|
||||
// Transmit shift register
|
||||
assign TransmitDataEndian = Format[0] ? {TransmitFIFOReadData[0], TransmitFIFOReadData[1], TransmitFIFOReadData[2], TransmitFIFOReadData[3], TransmitFIFOReadData[4], TransmitFIFOReadData[5], TransmitFIFOReadData[6], TransmitFIFOReadData[7]} : TransmitFIFOReadData[7:0];
|
||||
always_ff @(posedge PCLK)
|
||||
if(~PRESETn) TransmitShiftReg <= 8'b0; // Temporarily changing to 1s
|
||||
if(~PRESETn) TransmitShiftReg <= 8'b0;
|
||||
else if (TransmitShiftRegLoad) TransmitShiftReg <= TransmitDataEndian;
|
||||
else if (ShiftEdge & Active) TransmitShiftReg <= {TransmitShiftReg[6:0], TransmitShiftReg[0]}; // Temporarily changing to 1s
|
||||
else if (ShiftEdge & Active) TransmitShiftReg <= {TransmitShiftReg[6:0], TransmitShiftReg[0]};
|
||||
|
||||
assign SPIOut = TransmitShiftReg[7];
|
||||
|
||||
|
|
|
|||
|
|
@ -88,6 +88,8 @@
|
|||
|
||||
0000000B
|
||||
|
||||
000000F3
|
||||
|
||||
00000079
|
||||
|
||||
00000000
|
||||
|
|
|
|||
|
|
@ -178,6 +178,12 @@ test_cases:
|
|||
.4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
|
||||
.4byte rx_data, 0x0000000B, read32_test # read rx_data
|
||||
|
||||
# Test phase polarity
|
||||
.4byte sck_mode, 0x00000003, write32_test # set sck mode to 11
|
||||
.4byte tx_data, 0x000000F3, write32_test # place f3 into tx_data
|
||||
.4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
|
||||
.4byte rx_data, 0x000000F3, read32_test # read rx_data
|
||||
|
||||
# Test chip select polarity
|
||||
|
||||
.4byte sck_mode, 0x00000000, write32_test # reset sck polarity to active high
|
||||
|
|
@ -658,4 +664,4 @@ SETUP_PLIC
|
|||
|
||||
|
||||
|
||||
.4byte 0x0, 0x0, terminate_test
|
||||
.4byte 0x0, 0x0, terminate_test
|
||||
|
|
|
|||
|
|
@ -88,6 +88,8 @@
|
|||
00000000
|
||||
0000000B
|
||||
00000000
|
||||
000000F3
|
||||
00000000
|
||||
00000079
|
||||
00000000
|
||||
00000000
|
||||
|
|
|
|||
|
|
@ -180,6 +180,12 @@ test_cases:
|
|||
.8byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
|
||||
.8byte rx_data, 0x0000000B, read32_test # read rx_data
|
||||
|
||||
# Test phase polarity
|
||||
.8byte sck_mode, 0x00000003, write32_test # set sck mode to 11
|
||||
.8byte tx_data, 0x000000F3, write32_test # place f3 into tx_data
|
||||
.8byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
|
||||
.8byte rx_data, 0x000000F3, read32_test # read rx_data
|
||||
|
||||
# Test chip select polarity
|
||||
|
||||
.8byte sck_mode, 0x00000000, write32_test # reset sck polarity to active high
|
||||
|
|
@ -660,4 +666,4 @@ SETUP_PLIC
|
|||
|
||||
|
||||
|
||||
.8byte 0x0, 0x0, terminate_test
|
||||
.8byte 0x0, 0x0, terminate_test
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue