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More updates to fpga IP module names.

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This commit is contained in:
Rose Thompson 2024-08-22 14:31:39 -07:00
parent 8d40a0a092
commit fc80bf1251
12 changed files with 124 additions and 18 deletions
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10
fpga/constraints/marked_debug_rvvi.txt Normal file
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wally/wallypipelinedcore.sv: logic PCM
wally/wallypipelinedcore.sv: logic TrapM
wally/wallypipelinedcore.sv: logic InstrValidM
wally/wallypipelinedcore.sv: logic InstrM
lsu/lsu.sv: logic IEUAdrM
lsu/lsu.sv: logic PAdrM
lsu/lsu.sv: logic ReadDataM
lsu/lsu.sv: logic WriteDataM
lsu/lsu.sv: logic MemRWM
privileged/csrc.sv: logic HPMCOUNTER_REGW