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More updates to fpga IP module names.

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This commit is contained in:
Rose Thompson 2024-08-22 14:31:39 -07:00
parent 8d40a0a092
commit fc80bf1251
12 changed files with 124 additions and 18 deletions
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2
fpga/src/fpgaTopArtyA7.sv
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@ -400,7 +400,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
.m_axi_rready(BUS_axi_rready));
// DDR3 Controller
xlnx_ddr3 xlnx_ddr3_c0
ddr3 ddr3
(
// ddr3 I/O
.ddr3_dq(ddr3_dq),