mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-19 03:24:50 -04:00
Refactor imperas.ic files
This commit is contained in:
Jordan Carlin
parent
3e950a85c5
commit
ff4d3e7183
5 changed files with 86 additions and 224 deletions
3
bin/wsim
3
bin/wsim
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@ -121,6 +121,7 @@ def prepSim(args, ElfFile):
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return flags, prefix
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def lockstepSetup(args):
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imperasicSharedPath = os.path.join(WALLY, "config", "shared", "imperas-shared.ic")
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imperasicVerbosePath = os.path.join(WALLY, "sim", "imperas-verbose.ic")
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imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic")
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if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs
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@ -128,7 +129,7 @@ def lockstepSetup(args):
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if not os.path.isfile(imperasicPath):
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print("Error: imperas.ic not found")
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sys.exit(1)
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prefix = f"IMPERAS_TOOLS={imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''}"
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prefix = f"IMPERAS_TOOLS={imperasicSharedPath}:{imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''}"
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return prefix
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def createDirs(sim):
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@ -1,35 +1,16 @@
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# imperas.ic
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# Initialization file for ImperasDV lock step simulation
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# Initialization file for rv32gc ImperasDV lock step simulation
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# David_Harris@hmc.edu 15 August 2024
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# jcarlin@hmc.edu 19 March 2025
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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#--mpdconsole
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#--gdbconsole
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#--showoverrides
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#--showcommands
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# Core settings
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# Base configuration
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--variant RV32GCK # for RV32GC
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--override cpu/priv_version=1.12
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--override cpu/user_version=20191213
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# arch
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--override cpu/mimpid=0x100
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--override cpu/mvendorid=0x602
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--override cpu/marchid=0x24
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--override refRoot/cpu/tvec_align=64
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--override refRoot/cpu/envcfg_mask=1 # dh 1/26/24 this should be deleted when ImperasDV is updated to allow envcfg.FIOM to be written
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# bit manipulation
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# Bit manipulation
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--override cpu/add_Extensions=B
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--override cpu/bitmanip_version=1.0.0
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--override cpu/misa_B_Zba_Zbb_Zbs=T
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# More extensions
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--override cpu/Zcb=T
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--override cpu/Zicond=T
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--override cpu/Zfh=T
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--override cpu/Zfa=T
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# Cache block operations
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--override cpu/Zicbom=T
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--override cpu/Zicbop=T
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@ -38,78 +19,34 @@
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--override cmoz_bytes=64 # Zic64b
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--override lr_sc_grain=4 # Za64rs requires <=64; we use native word size
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# 64 KiB continuous huge pages supported
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#--override cpu/Svpbmt=F
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#--override cpu/Svnapot_page_mask=65536
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# SV32 supported
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--override cpu/Sv_modes=3
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#--showoverrides
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# Virtual memory
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--override cpu/Sv_modes=3 # SV32 supported
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--override cpu/Svadu=T # Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1
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--override cpu/Svinval=T
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# Crypto extensions
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--override cpu/Zkr=F # Zkr entropy source and seed register not supported.
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--override cpu/Zksed=F # ShangMi Crypto not supported
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--override cpu/Zksh=F # ShangMi Crypto not supported
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--override cpu/mnoise_undefined=T # nonratified mnoise register not implemented
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# clarify
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#--override refRoot/cpu/mtvec_sext=F
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--override cpu/tval_ii_code=T
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#--override cpu/time_undefined=T
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#--override cpu/cycle_undefined=T
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#--override cpu/instret_undefined=T
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#--override cpu/hpmcounter_undefined=T
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# context registers not implemented
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#--override cpu/scontext_undefined=True
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#--override cpu/mcontext_undefined=True
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# Disable all features that might want mseccfg or CSRs 7a0-7af
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--override cpu/Smepmp_version=none
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--override cpu/Smmpm=none
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#--override cpu/Zicfilp=F
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--override cpu/trigger_num=0 # disable CSRs 7a0-7a8
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# For code coverage, don't produce pseudoinstructions
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--override no_pseudo_inst=T
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# Show "c." with compressed instructions
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--override show_c_prefix=T
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# nonratified mnoise register not implemented
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--override cpu/mnoise_undefined=T
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# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
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#--override cpu/ecode_mask=0x8000000F # for RV32
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--override cpu/ecode_mask=0x800000000000000F # for RV64
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# Debug mode not yet supported
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--override cpu/debug_mode=none
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# Zkr entropy source and seed register not supported.
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--override cpu/Zkr=F
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# ShangMi Crypto not supported
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--override cpu/Zksed=F
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--override cpu/Zksh=F
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--override cpu/reset_address=0x80000000
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--override cpu/unaligned=F # Zicclsm (should be true)
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--override cpu/wfi_is_nop=T
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--override cpu/misa_Extensions_mask=0x0 # MISA not writable
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# Miscellaneous extensions
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--override cpu/Zicond=T
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--override cpu/Zfh=T
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--override cpu/Zfa=T
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--override cpu/Zcb=T
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--override cpu/Sstc=T
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# Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1
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--override cpu/Svadu=T
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#--override cpu/updatePTEA=F
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#--override cpu/updatePTED=F
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# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
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--override cpu/ecode_mask=0x8000000F # for RV32
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# Misaligned access (Zicclsm) is not supported
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--override cpu/unaligned=F
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# PMP Configuration
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--override cpu/PMP_registers=16
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--override cpu/PMP_undefined=T
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# mstatus.FS is set dirty on any write to a FPR, or when a fp operation signals an exception
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--override cpu/mstatus_fs_mode=write_1
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# PMA Settings
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# 'r': read access allowed
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# 'w': write access allowed
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@ -135,11 +72,3 @@
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--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO
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--callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI
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--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM
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# Enable the Imperas instruction coverage
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#-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
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#-override refRoot/cpu/cv/cover=basic
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#-override refRoot/cpu/cv/extensions=RV32I
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# Store simulator output to logfile
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--output imperas.log
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@ -1,22 +1,10 @@
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# imperas.ic
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# Initialization file for ImperasDV lock step simulation
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# David_Harris@hmc.edu 15 August 2024
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# Initialization file for rv32imc ImperasDV lock step simulation
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# jcarlin@hmc.edu 15 March 2025
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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#--mpdconsole
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#--gdbconsole
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#--showoverrides
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#--showcommands
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# Core settings
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# Base configuration
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--variant RV32IMC
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--override cpu/priv_version=1.12
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--override cpu/user_version=20191213
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# arch
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--override cpu/mimpid=0x100
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--override cpu/mvendorid=0x602
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--override cpu/marchid=0x24
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--override refRoot/cpu/tvec_align=64
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# No Supervisor mode
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--override cpu/sub_Extensions="S"
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@ -27,27 +15,9 @@
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# Little endian only
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--override cpu/endianFixed=T
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# For code coverage, don't produce pseudoinstructions
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--override no_pseudo_inst=T
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# Show "c." with compressed instructions
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--override show_c_prefix=T
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# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
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--override cpu/ecode_mask=0x8000000F # for RV32
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# disable CSRs 7a0-7a8
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--override cpu/trigger_num=0
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# Reset address
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--override cpu/reset_address=0x80000000
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# Wally implementats WFI as NOP
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--override cpu/wfi_is_nop=T
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# MISA not writable
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--override cpu/misa_Extensions_mask=0x0
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# No PMP
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--override cpu/PMP_registers=0
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--override cpu/PMP_undefined=T
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@ -75,6 +45,3 @@
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--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO
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--callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI
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--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x00807FFFFF -attributes " rwx--- 1248 " # DTIM/IROM
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# Store simulator output to logfile
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--output imperas.log
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@ -1,34 +1,16 @@
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# imperas.ic
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# Initialization file for ImperasDV lock step simulation
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# Initialization file for rv64gc ImperasDV lock step simulation
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# David_Harris@hmc.edu 15 August 2024
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# jcarlin@hmc.edu 19 March 2025
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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#--mpdconsole
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#--gdbconsole
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#--showoverrides
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#--showcommands
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# Base configuration
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--variant RV64GCK # for RV64GC
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# Core settings
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--override cpu/priv_version=1.12
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--override cpu/user_version=20191213
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# arch
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--override cpu/mimpid=0x100
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--override cpu/mvendorid=0x602
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--override cpu/marchid=0x24
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--override refRoot/cpu/tvec_align=64
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--override refRoot/cpu/envcfg_mask=1 # dh 1/26/24 this should be deleted when ImperasDV is updated to allow envcfg.FIOM to be written
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# bit manipulation
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# Bit manipulation
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--override cpu/add_Extensions=B
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--override cpu/bitmanip_version=1.0.0
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--override cpu/misa_B_Zba_Zbb_Zbs=T
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# More extensions
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--override cpu/Zcb=T
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--override cpu/Zicond=T
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--override cpu/Zfh=T
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--override cpu/Zfa=T
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# Cache block operations
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--override cpu/Zicbom=T
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--override cpu/Zicbop=T
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@ -37,78 +19,37 @@
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--override cmoz_bytes=64 # Zic64b
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--override lr_sc_grain=8 # Za64rs requires <=64; we use native word size
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# 64 KiB continuous huge pages supported
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# Virtual memory
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--override cpu/Sv_modes=768 # SV39 and SV48 supported
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--override cpu/Svadu=T # Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1
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--override cpu/Svinval=T
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--override cpu/Svpbmt=T
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--override cpu/aligned_uncached_PBMT=T # when PBMT designates a page as uncachable, require aligned accesses
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--override cpu/Svnapot_page_mask=65536
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--override cpu/Svnapot_page_mask=65536 # 64 KiB continuous huge pages supported
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# SV39 and SV48 supported
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--override cpu/Sv_modes=768
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# Crypto extensions
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--override cpu/Zkr=F # Zkr entropy source and seed register not supported.
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--override cpu/Zksed=F # ShangMi Crypto not supported
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--override cpu/Zksh=F # ShangMi Crypto not supported
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--override cpu/mnoise_undefined=T # nonratified mnoise register not implemented
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--override cpu/Svinval=T
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# clarify
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#--override refRoot/cpu/mtvec_sext=F
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--override cpu/tval_ii_code=T
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#--override cpu/time_undefined=T
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#--override cpu/cycle_undefined=T
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#--override cpu/instret_undefined=T
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#--override cpu/hpmcounter_undefined=T
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# context registers not implemented
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#--override cpu/scontext_undefined=True
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#--override cpu/mcontext_undefined=True
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# Disable all features that might want mseccfg or CSRs 7a0-7af
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--override cpu/Smepmp_version=none
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--override cpu/Smmpm=none
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#--override cpu/Zicfilp=F
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--override cpu/trigger_num=0 # disable CSRs 7a0-7a8
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# For code coverage, don't produce pseudoinstructions
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--override no_pseudo_inst=T
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# Show "c." with compressed instructions
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--override show_c_prefix=T
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# nonratified mnoise register not implemented
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--override cpu/mnoise_undefined=T
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# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
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#--override cpu/ecode_mask=0x8000000F # for RV32
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--override cpu/ecode_mask=0x800000000000000F # for RV64
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# Debug mode not yet supported
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--override cpu/debug_mode=none
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# Zkr entropy source and seed register not supported.
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--override cpu/Zkr=F
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# ShangMi Crypto not supported
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--override cpu/Zksed=F
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--override cpu/Zksh=F
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--override cpu/reset_address=0x80000000
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--override cpu/unaligned=T # Zicclsm (should be true)
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--override cpu/wfi_is_nop=T
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--override cpu/misa_Extensions_mask=0x0 # MISA not writable
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# Miscellaneous extensions
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--override cpu/Zicond=T
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--override cpu/Zfh=T
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--override cpu/Zfa=T
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--override cpu/Zcb=T
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--override cpu/Sstc=T
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# Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1
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--override cpu/Svadu=T
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#--override cpu/updatePTEA=F
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#--override cpu/updatePTED=F
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# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
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--override cpu/ecode_mask=0x800000000000000F # for RV64
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# Misaligned access (Zicclsm) is supported
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--override cpu/unaligned=T
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# PMP Configuration
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--override cpu/PMP_registers=16
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--override cpu/PMP_undefined=T
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# mstatus.FS is set dirty on any write to a FPR, or when a fp operation signals an exception
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--override cpu/mstatus_fs_mode=write_1
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# PMA Settings
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# 'r': read access allowed
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# 'w': write access allowed
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@ -134,11 +75,3 @@
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--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO
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--callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI
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--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM
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# Enable the Imperas instruction coverage
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#-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
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#-override refRoot/cpu/cv/cover=basic
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#-override refRoot/cpu/cv/extensions=RV32I
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# Store simulator output to logfile
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--output imperas.log
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32
config/shared/imperas-shared.ic
Normal file
32
config/shared/imperas-shared.ic
Normal file
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@ -0,0 +1,32 @@
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# imperas.ic
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# Standard initialization file for ImperasDV lock step simulation
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# jcarlin@hmc.edu 19 March 2025
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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# Spec versions
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--override cpu/priv_version=1.12
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--override cpu/user_version=20191213
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# arch
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--override cpu/mimpid=0x100
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--override cpu/mvendorid=0x602
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--override cpu/marchid=0x24
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--override refRoot/cpu/tvec_align=64
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# MISA not writable
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--override cpu/misa_Extensions_mask=0x0
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# disable CSRs 7a0-7a8
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--override cpu/trigger_num=0
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# Reset address
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--override cpu/reset_address=0x80000000
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# For code coverage, don't produce pseudoinstructions
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--override no_pseudo_inst=T
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# Show "c." with compressed instructions
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--override show_c_prefix=T
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# Store simulator output to logfile
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--output imperas.log
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