6 commits

Author	SHA1	Message	Date
Jordan Carlin	5271234591	Fix lots of spelling errors	2025-05-08 00:18:38 -07:00
Jordan Carlin	51c3d59605	Lots more python updates	2024-12-17 21:31:12 -08:00
Jordan Carlin	dfe15414b0	Lots more small python script cleanup	2024-12-17 15:30:05 -08:00
Jordan Carlin	b64f3f05f8	Revert changes to comment format now that preprocessor is being used	2024-10-18 16:03:56 -07:00
Jordan Carlin	638591e1dd	Update coverage test files. Assembler is picky and only accepts # comments and needs newlines	2024-10-18 16:03:55 -07:00
Alec Vercruysse	cd803bfa44	Cover CacheWay edge case: CacheDataMem we=1 while ce=0. ... This test basically triggers an i$ miss during a d$ (hit) store operation. It requires some tricky timing (e.g. a flushD right before the relevant store). I use a script to generate the test.	2023-04-19 01:34:01 -07:00