5 commits

Author	SHA1	Message	Date
Corey Hickson	6c651cd73e	Full cacheways code coverage	2025-04-17 02:28:20 -07:00
Jordan Carlin	b64f3f05f8	Revert changes to comment format now that preprocessor is being used	2024-10-18 16:03:56 -07:00
Jordan Carlin	638591e1dd	Update coverage test files. Assembler is picky and only accepts # comments and needs newlines	2024-10-18 16:03:55 -07:00
David Harris	45e2317636	Added Wally github address to header comments	2024-01-29 05:38:11 -08:00
Alec Vercruysse	b3a3af8ed3	add D$ test case to trigger a FlushStage while SetDirtyWay=1 ... This hits some conditional coverage in each cacheway. A cache store hit happens at the same time as a StoreAmoMisalignedFault.	2023-04-19 01:34:01 -07:00