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cvw/addins
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Jordan Carlin 05a47b2993
Bump riscv-arch-test
2025-04-06 17:12:50 -07:00
..
berkeley-softfloat-3@a0c6494cdc Bump addins/berkeley-softfloat-3 from 3b70b5d to a0c6494 2025-03-10 13:26:21 +00:00
berkeley-testfloat-3@a9c849f1b0 Bump addins/berkeley-testfloat-3 from 03c13d2 to a9c849f 2025-03-10 13:26:19 +00:00
branch-predictor-simulator@3e424e902f Swap in branch predictor simulator handling compressed instruction offsets 2023-11-21 16:42:41 -08:00
coremark@f3e8f2e094 added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug) 2022-06-13 23:23:57 +00:00
cvw-arch-verif@ce1b9c0f5b Remove a few more quad related files 2025-04-06 07:33:40 -07:00
embench-iot@54fd9a0f10 repo cleanup and start to add CMO tests 2023-11-20 23:41:36 -08:00
riscv-arch-test@3aa9b50e68 Bump riscv-arch-test 2025-04-06 17:12:50 -07:00
riscv-dv@f0c570d112 /cad/mentor/questa_sim-2023.4/questasim is fixed, relative paths to design and testbench files are fixed, and RISCV-DV submodule is updated back to the latest commit on master branch 2024-04-26 15:55:39 -07:00
verilog-ethernet@c180b22ed5 Revert "Bump addins/verilog-ethernet from c180b22 to 6f5ea41" 2024-11-26 08:15:36 -08:00
vivado-boards@d1898bd01f Bump addins/vivado-boards from 8ed4f99 to d1898bd 2025-01-06 14:07:12 +00:00
README.md Added some documenation about sparse-checkout for verilog-ethernet submodule. 2024-07-19 13:11:48 -05:00
sparse-checkout Cleanup in prep to merge the rvvi branch into main. 2024-07-19 15:48:20 -05:00

README.md

verilog-ethernet contains many ethernet devices. Wally's synthesizable RVVI interface only requires a small subset of these files. To do a sparse checkout of this repo copy sparse-checkout to cvw/.git/modules/addins/verilog-ethernet/info This will make the working directory only contain the necessary files.