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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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Noah Boorstin 117713be89 Linux test now gets through first 8 instructions! 
fixes the python parser:
  get the value, not function name, of PC
  only write changes to registers instead of registers every cycle
temporarilly NOP out CSRR instruction (with the canonical NOP), that was breaking this
dont stop on errors, print them prettier
2021-01-23 16:46:45 -05:00
riscv-o3@afb27bd558 Initial Checkin 2021-01-14 23:37:51 -05:00
wally-pipelined Linux test now gets through first 8 instructions! 2021-01-23 16:46:45 -05:00
.gitignore load instructions from file line by line 2021-01-22 14:11:17 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor