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cvw/fpga/src
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Jacob Pease f1cc7dd5a3 Fixed verilog bugs.
2024-07-23 17:26:39 -05:00
..
axi_sdc_controller.v Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock. 2023-10-10 17:46:12 -05:00
boot.mem Updated ROM to preload bootloader from file and infer a block ram when building for FPGA. 2023-11-18 19:15:39 -06:00
fpgaTop.sv Removed *** from fpga top. 2024-06-19 09:28:21 -07:00
fpgaTopArtyA7.sv Fixed verilog bugs. 2024-07-23 17:26:39 -05:00
wallypipelinedsocwrapper.sv Merge branch 'boot' into mergeBoot 2023-07-21 17:43:45 -05:00