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183 lines
4 KiB
ArmAsm
183 lines
4 KiB
ArmAsm
// pmpadrdecs
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// Liam Chalk, lchalk@hmc.edu, 4/27/2023
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// Setting AdrMode to 2 or 3 for pmpadrdecs[0-4]
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#include "WALLY-init-lib.h"
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main:
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# Writing values to pmpcfg0 to change AdrMode to 2 or 3
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# pmpadrdec[0]
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li t0, 0x0000000010
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csrw pmpcfg0, t0
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# pmpadrdec[1]
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li t0, 0x0000001800
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csrw pmpcfg0, t0
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# pmpadrdec[2]
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li t0, 0x0000180000
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csrw pmpcfg0, t0
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# pmpadrdec[4]
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li t0, 0x1000000000
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csrw pmpcfg0, t0
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# test hitting each region in NA4 mode for DMMU
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li t0, 0x20000000 # address 0x80000000
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csrw pmpaddr15, t0
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csrw pmpaddr14, t0
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csrw pmpaddr13, t0
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csrw pmpaddr12, t0
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li t0, 0x1717171717171717 # every region is NA4 XWR
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csrw pmpcfg0, t0
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csrw pmpcfg2, t0
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# test hitting region in NA4 mode for IMMU
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la t0, pmpjump # address of a jump destination to exercise immu pmpchecker
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srli t1, t0, 2 # shift right by 2 to convert to PMP format
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csrw pmpaddr15, t1
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csrw pmpaddr14, t1
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csrw pmpaddr13, t1
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csrw pmpaddr12, t1
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csrw pmpaddr11, t1
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csrw pmpaddr10, t1
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csrw pmpaddr9, t1
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csrw pmpaddr8, t1
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csrw pmpaddr7, t1
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csrw pmpaddr6, t1
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csrw pmpaddr5, t1
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csrw pmpaddr4, t1
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csrw pmpaddr3, t1
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csrw pmpaddr2, t1
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csrw pmpaddr1, t1
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csrw pmpaddr0, t1
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jalr t0
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# test hitting region in TOR mode for IMMU
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add t2, t1, 1 # top of range
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# region 0 TOR at pmpjump
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li t3, 0x0F # TOR XWR
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csrw pmpcfg0, t3
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csrw pmpcfg2, 0
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csrw pmpaddr0, t2
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jalr t0
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# region 1 TOR at pmpjump
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li t3, 0x0F00 # TOR XWR
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csrw pmpcfg0, t3
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csrw pmpcfg2, 0
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csrw pmpaddr0, t1
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csrw pmpaddr1, t2
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jalr t0
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# region 1 TOR at pmpjump
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li t3, 0x0F00 # TOR XWR
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csrw pmpcfg0, t3
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csrw pmpcfg2, 0
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csrw pmpaddr0, t1
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csrw pmpaddr1, t2
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jalr t0
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# region 8 TOR at pmpjump
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li t3, 0x0F # TOR XWR
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csrw pmpcfg2, t3
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csrw pmpcfg0, 0
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csrw pmpaddr7, t1
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csrw pmpaddr8, t2
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jalr t0
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# region 9 TOR at pmpjump
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li t3, 0x0F00 # TOR XWR
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csrw pmpcfg2, t3
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csrw pmpcfg0, 0
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csrw pmpaddr8, t1
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csrw pmpaddr9, t2
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jalr t0
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# region 10 TOR at pmpjump
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li t3, 0x0F0000 # TOR XWR
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csrw pmpcfg2, t3
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csrw pmpcfg0, 0
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csrw pmpaddr9, t1
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csrw pmpaddr10, t2
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jalr t0
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# region 11 TOR at pmpjump
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li t3, 0x0F000000 # TOR XWR
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csrw pmpcfg2, t3
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csrw pmpcfg0, 0
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csrw pmpaddr10, t1
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csrw pmpaddr11, t2
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jalr t0
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# region 12 TOR at pmpjump
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li t3, 0x0F00000000 # TOR XWR
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csrw pmpcfg2, t3
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csrw pmpcfg0, 0
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csrw pmpaddr11, t1
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csrw pmpaddr12, t2
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jalr t0
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# region 13 TOR at pmpjump
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li t3, 0x0F0000000000 # TOR XWR
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csrw pmpcfg2, t3
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csrw pmpcfg0, 0
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csrw pmpaddr12, t1
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csrw pmpaddr13, t2
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jalr t0
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# region 14 TOR at pmpjump
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li t3, 0x0F000000000000 # TOR XWR
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csrw pmpcfg2, t3
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csrw pmpcfg0, 0
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csrw pmpaddr13, t1
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csrw pmpaddr14, t2
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jalr t0
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# region 15 TOR at pmpjump
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li t3, 0x0F00000000000000 # TOR XWR
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csrw pmpcfg2, t3
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csrw pmpcfg0, 0
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csrw pmpaddr14, t1
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csrw pmpaddr15, t2
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jalr t0
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# test AMO not causing Load access fault
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# assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~WriteAccessM & ~MatchingR;
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la s0, scratch
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li t0, 0x0F000C00 # region 3 encompassing all addresses has TOR XWR, region 1 has TOR X only
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csrw pmpcfg0, t0
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# give only execute access to scratch
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# set up TOR region 0-1 to do this (yes, NA4 would work too)
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srli t0, s0, 2 # drop bottom two bits
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csrw pmpaddr0, t0
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addi t0, t0, 1 # next word
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csrw pmpaddr1, t0
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# everything else has full access, with a big TOR from 0 t0 FFFFFFFF
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csrw pmpaddr2, zero
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li t0, 0xFFFFFFFF # full range
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csrw pmpaddr3, t0
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# switch to supervisor mode
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li a0, 1
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ecall
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# test the AMO
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amoswap.w t1, zero, (s0) # attempt amo; should get store but not load access fault because this region is X only
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li a0, 3
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ecall # return to M mode
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j done
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.align 2
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pmpjump:
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ret
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.align 2
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scratch:
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.word 0
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