cvw/fpga/constraints/marked_debug.txt

wally/wallypipelinedcore.sv: logic             PCM
wally/wallypipelinedcore.sv: logic    TrapM
wally/wallypipelinedcore.sv: logic                InstrValidM
wally/wallypipelinedcore.sv: logic                 InstrM
lsu/lsu.sv: logic        IEUAdrM
lsu/lsu.sv: logic        PAdrM
lsu/lsu.sv: logic        ReadDataM
lsu/lsu.sv: logic        WriteDataM
lsu/lsu.sv: logic       MemRWM