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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

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David Harris 39d318fb2a Fixed path to riscvOVPsimPlus		2022-01-21 00:12:14 +00:00
addins	Added E extension, and downloaded riscv-dv and embench-iot to addins	2022-01-17 14:42:59 +00:00
benchmarks/riscv-coremark	Merged coremark changes	2022-01-10 05:09:28 +00:00
bin	Added E extension, and downloaded riscv-dv and embench-iot to addins	2022-01-17 14:42:59 +00:00
examples	Fixed path to riscvOVPsimPlus	2022-01-21 00:12:14 +00:00
fpga	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
linux	Created linux directory for linux config	2022-01-20 00:04:23 +00:00
pipelined	Fixed path to riscvOVPsimPlus	2022-01-21 00:12:14 +00:00
tests	moved fp to tests	2022-01-14 23:05:59 +00:00
.gitattributes	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
.gitignore	lsu cleanup down to 346 lines	2022-01-15 01:19:44 +00:00
.gitmodules	Added E extension, and downloaded riscv-dv and embench-iot to addins	2022-01-17 14:42:59 +00:00
LICENSE	Initial Checkin	2021-01-14 23:37:51 -05:00
Makefile	Fixed path to riscvOVPsimPlus	2022-01-21 00:12:14 +00:00
README.md	Update README.md	2022-01-05 11:29:54 -08:00
setup.sh	Code cleanup	2022-01-07 04:07:04 +00:00

README.md

riscv-wally

Configurable RISC-V Processor

Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.

See Chapter 2 of draft book of how to install and compile tests.