Rose Thompson 8d40a0a092 Changed names of fpga IP modules to match textbook. Updated boot.h to ... use the correct clock speed for #DEFINE for UART in the zero stage bootloader.		2024-08-22 13:56:50 -07:00
..
debug	Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.	2022-10-24 15:38:39 -05:00
bootrom.txt	Added bootrom.txt.	2022-03-30 17:29:48 -05:00
insert_debug_comment.sh	Maded insert_debug_comment.sh compatible with cygwin.	2024-04-22 10:48:34 -05:00
Makefile	Changed names of fpga IP modules to match textbook. Updated boot.h to	2024-08-22 13:56:50 -07:00
probe	Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability)	2024-07-03 20:42:55 -07:00
wally.tcl	Changed names of fpga IP modules to match textbook. Updated boot.h to	2024-08-22 13:56:50 -07:00
wave_config.wcfg	Updateds to vcu118 constraints and device tree.	2023-08-02 16:51:32 -05:00
xlnx_ddr3-artya7-mig.prj	It's almost working.	2023-04-18 14:24:59 -05:00
xlnx_ddr3-ArtyA7.tcl	Finally fixed the ddr3 mig script to work correclty.	2023-04-14 11:41:51 -05:00
xlnx_ddr4-vcu108.tcl	Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.	2022-10-24 15:38:39 -05:00
xlnx_ddr4-vcu118.tcl	Pushed vcu118 to 71MHz.	2023-08-25 17:04:50 -05:00
xlnx_ddr4.tcl	Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.	2022-10-24 15:38:39 -05:00