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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

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Ross Thompson 9150133c7d Fpga simualtion files.		2021-10-11 10:24:40 -05:00
fpga/sim	Fpga simualtion files.	2021-10-11 10:24:40 -05:00
riscv-coremark	Made a backup folder accessible to everyone for 3 portme directories that would not be preserved in the case of a clean coremark installation.	2021-08-12 05:23:04 -04:00
testsBP	added support to due partial fpga simulation.	2021-09-26 15:00:00 -05:00
wally-pipelined	Fpga simualtion files.	2021-10-11 10:24:40 -05:00
.gitattributes	moved shared constants to a shared directory	2021-06-03 22:41:30 -04:00
.gitignore	Updated ignore file.	2021-09-24 18:48:45 -05:00
.gitmodules	Flow updated for 90nm	2021-07-01 13:32:42 -05:00
LICENSE	Initial Checkin	2021-01-14 23:37:51 -05:00
README.md	Initial commit	2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor