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108 lines
4.5 KiB
Python
Executable file
108 lines
4.5 KiB
Python
Executable file
#!/usr/bin/python
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##################################################
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## coremark_sweep.py
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## Written: Shreesh Kulkarni, kshreesh5@gmail.com
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## Created: 20 March 2024
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## Modified: 22 March 2024
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## Purpose: Wally Coremark sweep Script for both 32 and 64 bit configs with csv file extraction.
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## Documentation:
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# A component of the CORE-V-WALLY configurable RISC-V project.
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# https://github.com/openhwgroup/cvw
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# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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#
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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# except in compliance with the License, or, at your option, the Apache License version 2.0. You
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# may obtain a copy of the License at
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# https://solderpad.org/licenses/SHL-2.1/
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# Unless required by applicable law or agreed to in writing, any work distributed under the
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# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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# either express or implied. See the License for the specific language governing permissions
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# and limitations under the License.
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###########################################################################################
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import os
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import re
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import csv
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# list of architectures to run.
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arch32_list = [
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"rv32gc_zba_zbb_zbc",
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"rv32im_zicsr_zba_zbb_zbc",
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"rv32gc",
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"rv32imc_zicsr",
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"rv32im_zicsr",
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"rv32i_zicsr"
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]
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#uncomment this array for 64bit configurations
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#arch64_list = [
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# "rv64gc_zba_zbb_zbc",
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# "rv64im_zicsr_zba_zbb_zbc",
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# "rv64gc",
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# "rv64imc_zicsr",
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# "rv64im_zicsr",
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# "rv64i_zicsr"
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#]
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xlen_value = '32'
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#xlen_value = '64' #uncomment this for 64 bit.
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# Define regular expressions to match the desired fields
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mt_regex = r"Elapsed MTIME: (\d+).*?Elapsed MINSTRET: (\d+).*?COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+).*?CPI: \d+ / \d+ = (\d+\.\d+).*?Load Stalls (\d+).*?Store Stalls (\d+).*?D-Cache Accesses (\d+).*?D-Cache Misses (\d+).*?I-Cache Accesses (\d+).*?I-Cache Misses (\d+).*?Branches (\d+).*?Branches Miss Predictions (\d+).*?BTB Misses (\d+).*?Jump and JR (\d+).*?RAS Wrong (\d+).*?Returns (\d+).*?BP Class Wrong (\d+)"
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#cpi_regex = r"CPI: \d+ / \d+ = (\d+\.\d+)"
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#cmhz_regex = r"COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+)"
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# Open a CSV file to write the results
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with open('coremark_results.csv', mode='w', newline='') as csvfile:
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fieldnames = ['Architecture', 'MTIME','MINSTRET','CM / MHz','CPI','Load Stalls','Store Stalls','D$ Accesses',
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'D$ Misses','I$ Accesses','I$ Misses','Branches','Branch Mispredicts','BTB Misses',
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'Jump/JR','RAS Wrong','Returns','BP Class Pred Wrong']
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writer = csv.DictWriter(csvfile, fieldnames=fieldnames)
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writer.writeheader()
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# Loop through each architecture and run the make commands
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for arch in arch32_list:
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os.system("make clean")
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make_all = f"make all XLEN={xlen_value} ARCH={arch}"
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os.system(make_all)
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make_run = f"make run XLEN={xlen_value} ARCH={arch}"
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print("Running: " + make_run)
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output = os.popen(make_run).read() # Capture the output of the command
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# Extract the Coremark values using regular expressions
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mt_match = re.search(mt_regex, output,re.DOTALL)
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#cpi_match = re.search(cpi_regex,output,re.DOTALL)
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#cmhz_match = re.search(cmhz_regex,output,re.DOTALL)
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#minstret_match = re.search(minstret_regex,output)
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# Write the architecture and extracted values to the CSV file
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mtime = mt_match.group(1)
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minstret= mt_match.group(2)
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cmhz= mt_match.group(3)
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cpi= mt_match.group(4)
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lstalls= mt_match.group(5)
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swtalls= mt_match.group(6)
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dacc= mt_match.group(7)
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dmiss= mt_match.group(8)
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iacc= mt_match.group(9)
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imiss= mt_match.group(10)
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br= mt_match.group(11)
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brm= mt_match.group(12)
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btb= mt_match.group(13)
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jmp= mt_match.group(14)
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ras= mt_match.group(15)
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ret= mt_match.group(16)
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bpc= mt_match.group(17)
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#minstret = mt_instret_match.group(2)
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writer.writerow({'Architecture': arch, 'MTIME': mtime,'MINSTRET':minstret,'CM / MHz':cmhz,'CPI':cpi,
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'Load Stalls':lstalls,
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'Store Stalls':swtalls,'D$ Accesses':dacc,'D$ Misses':dmiss,'I$ Accesses':iacc,'I$ Misses':imiss,
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'Branches':br,'Branch Mispredicts':brm,'BTB Misses':btb,'Jump/JR':jmp,'RAS Wrong':ras,'Returns':ret,'BP Class Pred Wrong':bpc})
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