Rose Thompson bb0c663707 Added in David's testbench check for traps without a trap handler. Generates an error message and stops simulation.		2025-05-04 12:21:23 -05:00
..
common	Fixed order counter in RVVI interface, resolving Issue #1304	2025-04-24 10:50:16 -07:00
sdc	Enable ruff import sorting	2025-02-15 15:44:24 -08:00
trek_files	Breker optimizations	2025-03-28 13:39:17 -07:00
Makefile	Add Makefile in testbench to allow the memfile to generate the correct version based on the elf output in objdump. Previously this was done via a findstring which works with riscv-arch-tests but doesn't allow individual programs/elf to be used unless the program is called xxx_rv32.	2025-01-24 08:55:25 -06:00
testbench.sv	Added in David's testbench check for traps without a trap handler. Generates an error message and stops simulation.	2025-05-04 12:21:23 -05:00
testbench_fp.sv	Restore testbench_fp to load from vectors directory	2024-09-29 00:57:41 -07:00
tests.vh	Fixed Issue #1321 about wally32periph failing on rv32imc; removed SEIP tests from WALLY-periph-01 and put them in WALY-periph-s	2025-04-12 20:32:51 -07:00
tests_fp.vh	Restore testbench_fp to load from vectors directory	2024-09-29 00:57:41 -07:00
wallywrapper.sv	Merge branch 'main' of github.com:openhwgroup/cvw into spiboot	2024-08-06 17:09:39 -05:00