SadhviNarayanan df1a787c60 removed rv64gc python cache script, updated testbench.sv		2025-05-10 13:36:10 -07:00
..
common	minor code changes and optimizations	2025-05-10 10:21:47 -07:00
sdc	Fix lots of spelling errors	2025-05-08 00:18:38 -07:00
trek_files	Fix lots of spelling errors	2025-05-08 00:18:38 -07:00
Makefile	Add Makefile in testbench to allow the memfile to generate the correct version based on the elf output in objdump. Previously this was done via a findstring which works with riscv-arch-tests but doesn't allow individual programs/elf to be used unless the program is called xxx_rv32.	2025-01-24 08:55:25 -06:00
testbench.sv	removed rv64gc python cache script, updated testbench.sv	2025-05-10 13:36:10 -07:00
testbench_fp.sv	Fix lots of spelling errors	2025-05-08 00:18:38 -07:00
tests.vh	Fix lots of spelling errors	2025-05-08 00:18:38 -07:00
tests_fp.vh	Restore testbench_fp to load from vectors directory	2024-09-29 00:57:41 -07:00
wallywrapper.sv	Merge branch 'main' of github.com:openhwgroup/cvw into spiboot	2024-08-06 17:09:39 -05:00