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79 lines
3.5 KiB
Systemverilog
79 lines
3.5 KiB
Systemverilog
///////////////////////////////////////////
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// resultsign.sv
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//
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// Written: me@KatherineParry.com
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// Modified: 7/5/2022
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//
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// Purpose: calculating the result's sign
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//
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// Documentation: RISC-V System on Chip Design
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module resultsign(
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input logic [2:0] Frm, // rounding mode
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input logic FmaOp, // is the operation an Fma
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input logic Mult, // is the fma operation multiply
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input logic ZInf, // is Z infinity
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input logic InfIn, // are any of the inputs infinity
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input logic FmaSZero, // is the fma sum zero
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input logic Ms, // normalized result sign
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input logic FmaPs, // product's sign
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input logic FmaAs, // aligned addend's sign
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input logic Guard, // guard bit for rounding
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input logic Round, // round bit for rounding
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input logic Sticky, // sticky bit for rounding
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output logic Rs // result sign
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);
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logic Zeros; // zero result sign
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logic Infs; // infinity result sign
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// determine the sign for a result of 0
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// The IEEE754-2019 standard specifies:
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// - the sign of an exact zero sum (with operands of different signs) should be positive unless rounding toward negative infinity
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// - when the exact result of an FMA operation is non-zero, but is zero due to rounding, use the sign of the exact result
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// - if x = +0 or -0 then x+x=x and x-(-x)=x
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// - the sign of a product is the exclisive or or the opperand's signs
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// Zero sign will only be selected if:
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// - P=Z and a cancellation occurs - exact zero
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// - Z is zero and P is zero - exact zero
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// - P is killed and Z is zero - Psgn
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// - Z is killed and P is zero - impossible
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// Zero sign calculation:
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// - if a multiply operation is done, then use the products sign(Ps)
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// - if the zero sum is not exactly zero i.e. Round|Sticky use the sign of the exact result (which is the product's sign)
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// - if an effective addition occurs (P+A or -P+-A or P--A) then use the product's sign
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assign Zeros = (FmaPs^FmaAs)&~(Round|Guard|Sticky)&~Mult ? Frm[1:0] == 2'b10 : FmaPs;
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// determine the sign of an infinity result
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// is the result negative
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// if p - z is the Sum negative
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// if -p + z is the Sum positive
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// if -p - z then the Sum is negative
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assign Infs = ZInf ? FmaAs : FmaPs;
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// select the result sign
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always_comb
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if(InfIn&FmaOp) Rs = Infs;
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else if(FmaSZero&FmaOp) Rs = Zeros;
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else Rs = Ms;
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endmodule
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