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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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Noah Boorstin e45f452f25 Start adding register checking 
I'm now realizing we need to simulate loads, or else these will all be wrong
2021-01-22 15:11:13 -05:00
riscv-o3@afb27bd558 Initial Checkin 2021-01-14 23:37:51 -05:00
wally-pipelined Start adding register checking 2021-01-22 15:11:13 -05:00
.gitignore load instructions from file line by line 2021-01-22 14:11:17 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor