mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-06-28 17:43:09 -04:00
118 lines
8.7 KiB
Tcl
118 lines
8.7 KiB
Tcl
create_debug_core u_ila_0 ila
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set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
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set_property C_TRIGIN_EN true [get_debug_cores u_ila_0]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
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set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
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set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
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set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
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create_debug_port u_ila_0 trig_in
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create_debug_port u_ila_0 trig_in_ack
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#set_property port_width 1 [get_debug_ports u_ila_0/trig_in]
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#set_property port_width 1 [get_debug_ports u_ila_0/trig_in_ack]
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#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/trig_in]
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connect_debug_port u_ila_0/trig_in [get_nets IlaTrigger]
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#connect_debug_port u_ila_0/trig_in_ack [get_nets IlaTriggerAck]
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connect_debug_port u_ila_0/clk [get_nets CPUCLK]
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set_property port_width 32 [get_debug_ports u_ila_0/probe0]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
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connect_debug_port u_ila_0/probe0 [get_nets [list {RvviAxiRdata[0]} {RvviAxiRdata[1]} {RvviAxiRdata[2]} {RvviAxiRdata[3]} {RvviAxiRdata[4]} {RvviAxiRdata[5]} {RvviAxiRdata[6]} {RvviAxiRdata[7]} {RvviAxiRdata[8]} {RvviAxiRdata[9]} {RvviAxiRdata[10]} {RvviAxiRdata[11]} {RvviAxiRdata[12]} {RvviAxiRdata[13]} {RvviAxiRdata[14]} {RvviAxiRdata[15]} {RvviAxiRdata[16]} {RvviAxiRdata[17]} {RvviAxiRdata[18]} {RvviAxiRdata[19]} {RvviAxiRdata[20]} {RvviAxiRdata[21]} {RvviAxiRdata[22]} {RvviAxiRdata[23]} {RvviAxiRdata[24]} {RvviAxiRdata[25]} {RvviAxiRdata[26]} {RvviAxiRdata[27]} {RvviAxiRdata[28]} {RvviAxiRdata[29]} {RvviAxiRdata[30]} {RvviAxiRdata[31]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe1]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
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connect_debug_port u_ila_0/probe1 [get_nets [list RvviAxiWlast ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe2]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
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connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
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create_debug_port u_ila_0 probe
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set_property port_width 4 [get_debug_ports u_ila_0/probe3]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
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connect_debug_port u_ila_0/probe3 [get_nets [list {ethernet/eth_mac_1g_mii_inst/mii_phy_if_inst/mac_mii_txd[0]} {ethernet/eth_mac_1g_mii_inst/mii_phy_if_inst/mac_mii_txd[1]} {ethernet/eth_mac_1g_mii_inst/mii_phy_if_inst/mac_mii_txd[2]} {ethernet/eth_mac_1g_mii_inst/mii_phy_if_inst/mac_mii_txd[3]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 4 [get_debug_ports u_ila_0/probe4]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
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connect_debug_port u_ila_0/probe4 [get_nets [list {packetizer/CurrState[0]} {packetizer/CurrState[1]} {packetizer/CurrState[2]} {packetizer/CurrState[3]}]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe5]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
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connect_debug_port u_ila_0/probe5 [get_nets [list {ethernet/eth_mac_1g_mii_inst/mii_phy_if_inst/mac_mii_tx_en} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 64 [get_debug_ports u_ila_0/probe6]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
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connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
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#create_debug_port u_ila_0 probe
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#set_property port_width 1 [get_debug_ports u_ila_0/probe7]
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#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
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#connect_debug_port u_ila_0/probe7 [get_nets [list {IlaTrigger} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe7]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
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connect_debug_port u_ila_0/probe7 [get_nets [list {RvviAxiWvalid}]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe8]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
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connect_debug_port u_ila_0/probe8 [get_nets [list {RVVIStall}]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe9]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
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connect_debug_port u_ila_0/probe9 [get_nets [list {valid}]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe10]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
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connect_debug_port u_ila_0/probe10 [get_nets [list {RvviAxiWready}]]
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create_debug_port u_ila_0 probe
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set_property port_width 3 [get_debug_ports u_ila_0/probe11]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
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connect_debug_port u_ila_0/probe11 [get_nets [list {triggergen/CurrState[0]} {triggergen/CurrState[1]} {triggergen/CurrState[2]}]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe12]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
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connect_debug_port u_ila_0/probe12 [get_nets [list {RvviAxiRlast}]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe13]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
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connect_debug_port u_ila_0/probe13 [get_nets [list {RvviAxiRvalid}]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe14]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
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connect_debug_port u_ila_0/probe14 [get_nets [list {triggergen/IlaTriggerOneCycle}]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe15]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
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connect_debug_port u_ila_0/probe15 [get_nets [list {triggergen/TriggerReset}]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe16]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
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connect_debug_port u_ila_0/probe16 [get_nets [list {triggergen/TriggerEn}]]
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create_debug_port u_ila_0 probe
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set_property port_width 4 [get_debug_ports u_ila_0/probe17]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
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connect_debug_port u_ila_0/probe17 [get_nets [list {triggergen/TriggerCount[0]} {triggergen/TriggerCount[1]} {triggergen/TriggerCount[2]} {triggergen/TriggerCount[3]}]]
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# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
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#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
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connect_debug_port dbg_hub/clk [get_nets CPUCLK]
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