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30 lines
1.4 KiB
Tcl
30 lines
1.4 KiB
Tcl
set partNumber xc7a100tcsg324-1
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set boardName arty-a7
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set ipName xlnx_ddr3
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create_project $ipName . -force -part $partNumber
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#set_property board_part $boardName [current_project]
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# really just these two lines which change
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create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName
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# to recreate one of these.
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# 1. use the gui to generate a mig.
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# 2. Find the xci file in project_1/project_1.srcs/sources_1/ip/mig_7series_0/
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# 3. Run vivado in tcl mode and use command list_property [get_ips $ipName]
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# to find all parameters for this ip.
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# 4. Then reconstruct the list with the needed parameters.
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# turns out the ddr3 mig cannot be built this way like the ddr 4 mig?!?!?
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# instead we need to read the project file, but we have to copy it to the corret location first
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cp $WALLY/fpga/generator/xlnx_ddr3-artya7-mig.prj IP/xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/
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# unlike the vertex ultra scale and ultra scale + fpga's the atrix 7 mig we only get ui clock.
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set_property -dict [list CONFIG.XML_INPUT_FILE {xlnx_ddr3-artya7-mig.prj}] [get_ips $ipName]
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generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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launch_run -jobs 8 ${ipName}_synth_1
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wait_on_run ${ipName}_synth_1
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