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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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Noah Boorstin f1768ee50b Busybear: start checking CSRs 
scounteren and mcounteren are currenly manually deleted from the CSRs list
(see slack channl #linux-bringup)

and 3 of the CSRs referenced are skipped because of weird locations for them

oh and this doesn't check their initial state, just their changing. This could be a problem
2021-02-02 06:06:03 +00:00
riscv-o3@afb27bd558 Hint to optimize ifu 2021-01-28 21:40:48 -05:00
sky130 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
wally-pipelined Busybear: start checking CSRs 2021-02-02 06:06:03 +00:00
.gitignore Busybear test now processes first 100 instrs correctly! 2021-01-28 01:19:27 -05:00
.gitmodules Added synth and PnR flow 2021-01-25 14:28:14 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor