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Simple RV32I validation assembly code
This commit is contained in:
Douglas Santos
parent
2d54e7cbc2
commit
bc5edd7d16
2 changed files with 201 additions and 7 deletions
171
src/rv32i.asm
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171
src/rv32i.asm
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@ -0,0 +1,171 @@
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.data
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var0: 100
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res_auipc: 0x00020008
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res_lui: 0x00020000
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res_li: 0x00000194
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res_add: 350
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res_slt: 1
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res_xor: 158
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res_sll: 800
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res_srl: 12
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res_or: 254
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res_and: 96
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res_jal: 0x000000CA
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# assembly code to validate entire rv32i
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.text
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j start
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error:
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j error
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start:
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# add upper immediate to PC
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auipc t0, 0x20
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lw t1, res_auipc
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bne t0, t1, error
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# load upper immediate
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lui t0, 0x20
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lw t1, res_lui
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bne t0, t1, error
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# TODO: asserts to ensure that the first instructions work
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# load and store words
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la a0, var0
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lw t0, 0(a0)
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sw t0, 0(a0)
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lw t1, 0(a0)
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bne t0, t1, error
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# TODO: load and store half-words and bytes
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# add immediate
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addi t0, x0, 0xCA
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addi t0, t0, 0xCA
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lw t1, res_li
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bne t0, t1, error
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# initalize variables for next operations
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li a0, 100
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li a1, 250
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li a2, 3
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# add
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add t0, a0, a1
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lw t1, res_add
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bne t0, t1, error
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# set on less than
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slt t0, a0, a1
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lw t1, res_slt
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bne t0, t1, error
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# TODO: sltu
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# exclusive-or
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xor t0, a0, a1
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lw t1, res_xor
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bne t0, t1, error
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# shift left logical
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sll t0, a0, a2
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lw t1, res_sll
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bne t0, t1, error
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# shift right logical
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srl t0, a0, a2
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lw t1, res_srl
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bne t0, t1, error
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# shift right arithmetic
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sra t0, a0, a2
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lw t1, res_srl
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bne t0, t1, error
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# or
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or t0, a0, a1
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lw t1, res_or
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bne t0, t1, error
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# and
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and t0, a0, a1
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lw t1, res_and
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bne t0, t1, error
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# jump and link
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jal ra, jal_test
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lw t1, res_jal
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bne t0, t1, error
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j jal_continue
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jal_test:
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addi t0, x0, 0xCA
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jalr x0, ra, 0
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jal_continue:
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# branch on equal
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# test: take branch
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li t0, 0x100
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li t1, 0x100
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beq t0, t1, equal0
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j error
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equal0:
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# test: dont take branch
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li t0, 0x100
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li t1, 0x101
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beq t0, t1, equal1
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j beq_continue
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equal1:
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j error
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beq_continue:
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# branch on not equal
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# test: take branch
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li t0, 0x100
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li t1, 0x101
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bne t0, t1, not_equal0
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j error
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not_equal0:
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# test: dont take branch
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li t0, 0x100
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li t1, 0x100
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bne t0, t1, not_equal1
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j bne_continue
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not_equal1:
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j error
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bne_continue:
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# branch on less than
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# test: take branch
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li t0, -0x10
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li t1, 0x10
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blt t0, t1, less0
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j error
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less0:
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# test: dont take branch
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li t0, 0x10
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li t1, 0x10
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blt t0, t1, less1
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j blt_continue
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less1:
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j error
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blt_continue:
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# branch on greater or equal
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# test: take branch
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li t0, 0x10
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li t1, 0x10
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bge t0, t1, greater0
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j error
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greater0:
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# test: dont take branch
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li t0, -0x10
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li t1, 0x10
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bge t0, t1, greater1
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j bge_continue
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greater1:
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j error
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bge_continue:
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# TODO: bltu, bgeu
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success:
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j success
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@ -12,15 +12,15 @@
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</db_ref>
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</db_ref_list>
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<zoom_setting>
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<ZoomStartTime time="0fs"></ZoomStartTime>
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<ZoomEndTime time="4890001fs"></ZoomEndTime>
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<Cursor1Time time="2070000fs"></Cursor1Time>
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<ZoomStartTime time="42035834fs"></ZoomStartTime>
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<ZoomEndTime time="44520835fs"></ZoomEndTime>
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<Cursor1Time time="43030834fs"></Cursor1Time>
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</zoom_setting>
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<column_width_setting>
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<NameColumnWidth column_width="204"></NameColumnWidth>
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<NameColumnWidth column_width="196"></NameColumnWidth>
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<ValueColumnWidth column_width="66"></ValueColumnWidth>
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</column_width_setting>
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<WVObjectSize size="28" />
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<WVObjectSize size="34" />
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<wvobject type="array" fp_name="/sim_from_dump/INST_DUMP_FILE_PATH">
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<obj_property name="ElementShortName">INST_DUMP_FILE_PATH[1:33]</obj_property>
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<obj_property name="ObjectShortName">INST_DUMP_FILE_PATH[1:33]</obj_property>
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@ -90,7 +90,7 @@
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<obj_property name="ElementShortName">[5][31:0]</obj_property>
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<obj_property name="ObjectShortName">[5][31:0]</obj_property>
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<obj_property name="label">reg_t0</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/sim_from_dump/harv_i/regfile_i/g_normal/regfile_w">
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<obj_property name="ElementShortName">regfile_w[31:0][31:0]</obj_property>
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@ -112,6 +112,30 @@
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<obj_property name="ElementShortName">wren_i</obj_property>
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<obj_property name="ObjectShortName">wren_i</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/sim_from_dump/harv_i/instr_fetch_i/jump_i">
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<obj_property name="ElementShortName">jump_i</obj_property>
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<obj_property name="ObjectShortName">jump_i</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/sim_from_dump/harv_i/instr_fetch_i/jump_imm_i">
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<obj_property name="ElementShortName">jump_imm_i[31:0]</obj_property>
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<obj_property name="ObjectShortName">jump_imm_i[31:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/sim_from_dump/harv_i/imm_i_w">
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<obj_property name="ElementShortName">imm_i_w[11:0]</obj_property>
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<obj_property name="ObjectShortName">imm_i_w[11:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/sim_from_dump/harv_i/imm_w">
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<obj_property name="ElementShortName">imm_w[31:0]</obj_property>
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<obj_property name="ObjectShortName">imm_w[31:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/sim_from_dump/harv_i/ctl_aluop_w">
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<obj_property name="ElementShortName">ctl_aluop_w[3:0]</obj_property>
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<obj_property name="ObjectShortName">ctl_aluop_w[3:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/sim_from_dump/harv_i/alu_data_w">
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<obj_property name="ElementShortName">alu_data_w[31:0]</obj_property>
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<obj_property name="ObjectShortName">alu_data_w[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="divider12648" type="divider">
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<obj_property name="label">MEMORIES</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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@ -143,7 +167,6 @@
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<wvobject type="group" fp_name="group4275">
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<obj_property name="label">dmem</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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<obj_property name="isExpanded"></obj_property>
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<wvobject type="array" fp_name="/sim_from_dump/dmem_data_i">
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<obj_property name="ElementShortName">dmem_data_i[31:0]</obj_property>
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<obj_property name="ObjectShortName">dmem_data_i[31:0]</obj_property>
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