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Removed board part definition in Xilinx project creation script

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Douglas Santos 2022-03-10 19:29:18 +01:00
parent fd29cd36f0
commit d16ffe250e
1 changed files with 0 additions and 1 deletions
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script/project.tcl
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@ -168,7 +168,6 @@ set proj_dir [get_property directory [current_project]]
# Set project properties
set obj [current_project]
set_property -name "board_part" -value "em.avnet.com:zed:part0:1.4" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj