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Arithmetic shift right bug fixed

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This commit is contained in:
Douglas Santos 2022-02-04 17:58:33 +01:00
parent 8f2b766130
commit fd29cd36f0
1 changed files with 9 additions and 6 deletions
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13
hdl/control.vhd
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@ -109,6 +109,8 @@ architecture arch of control is
-- signal rshift_op_w : std_logic_vector(ALUOP_SIZE-1 downto 0);
-- signal add_op_w : std_logic_vector(ALUOP_SIZE-1 downto 0);
signal shift_op_w : std_logic;
signal add_sub_op_w : std_logic;
signal aluop_w : std_logic_vector(ALUOP_SIZE-1 downto 0);
signal branch_op_w : std_logic_vector(ALUOP_SIZE-1 downto 0);
@ -209,8 +211,11 @@ begin
ALU_SLTU_OP when "11", -- bltu or bgeu
ALU_XOR_OP when others; -- not in specification
aluop_w <= "0" & funct3_i when instr_format_w = I_arith else
funct7_i(5) & funct3_i when instr_format_w = R else
shift_op_w <= '1' when funct3_i(1 downto 0) = "01" else '0';
add_sub_op_w <= '1' when funct3_i = "000" else '0';
aluop_w <= (funct7_i(5) and shift_op_w) & funct3_i when instr_format_w = I_arith else
(funct7_i(5) and (shift_op_w or add_sub_op_w)) & funct3_i when instr_format_w = R else
branch_op_w when instr_format_w = B else
ALU_ADD_OP; -- when instr_format_w = U_auipc, I_load, S
aluop_o <= aluop_w;
@ -218,9 +223,7 @@ begin
------------------------ IMMEDIATE SELECTOR ------------------------------
-- instr[24:20]
imm_shamt_o <= '1' when (aluop_w = ALU_SLL_OP or
aluop_w = ALU_SRL_OP or
aluop_w = ALU_SRA_OP) else '0';
imm_shamt_o <= '1' when (instr_format_w = I_arith or instr_format_w = R) and shift_op_w = '1' else '0';
-- instr[31:12] -> imm[31:12]
imm_up_o <= '1' when instr_format_w = U_lui or
instr_format_w = U_auipc else '0';