[dv] Increase generated CSR instructions in riscv_rand_instr_test

This employs new RISC-V DV functionality to better stimulate reads and
writes for various CSRs in the random instruction test.

dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv

@@ -11,6 +11,47 @@ class ibex_asm_program_gen extends riscv_asm_program_gen;
   `uvm_object_utils(ibex_asm_program_gen)
   `uvm_object_new
 
+  virtual function void gen_program();
+    default_include_csr_write = {
+      MSCRATCH,
+      MVENDORID,
+      MARCHID,
+      MHARTID,
+      MIMPID,
+      MCYCLE,
+      MCYCLEH,
+      MHPMEVENT3,
+      MHPMEVENT4,
+      MHPMEVENT5,
+      MHPMEVENT6,
+      MHPMEVENT7,
+      MHPMEVENT8,
+      MHPMEVENT9,
+      MHPMEVENT10,
+      MHPMCOUNTER3,
+      MHPMCOUNTER4,
+      MHPMCOUNTER5,
+      MHPMCOUNTER6,
+      MHPMCOUNTER7,
+      MHPMCOUNTER8,
+      MHPMCOUNTER9,
+      MHPMCOUNTER10,
+      MHPMCOUNTER3H,
+      MHPMCOUNTER4H,
+      MHPMCOUNTER5H,
+      MHPMCOUNTER6H,
+      MHPMCOUNTER7H,
+      MHPMCOUNTER8H,
+      MHPMCOUNTER9H,
+      MHPMCOUNTER10H,
+      12'h7c1 // SECURESEED
+    };
+
+    riscv_csr_instr::create_csr_filter(cfg);
+
+    super.gen_program();
+  endfunction
+
   virtual function void gen_program_header();
     // Override the mstatus_mprv config because there is no current way to randomize writing to
     // mstatus.mprv in riscv-dv (it's constrained by set_mstatus_mprv argument to have either

dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv

@@ -111,9 +111,13 @@ int kernel_program_instr_cnt = 400;
 // ----------------------------------------------------------------------------
 
 // Implemented previlieged CSR list
+// TODO: Bring back commented out CSRs, these are currently removed as they can
+// cause co-sim mismatches. These must be investigated and fixed
 const privileged_reg_t implemented_csr[] = {
     // Machine mode mode CSR
+    MSCRATCH,         // Scratch register
     MVENDORID,        // Vendor ID
+    MIMPID,           // Implementation ID
     MARCHID,          // Architecture ID
     MHARTID,          // Hardware thread ID
     MSTATUS,          // Machine status
@@ -126,8 +130,8 @@ const privileged_reg_t implemented_csr[] = {
     MIP,              // Machine interrupt pending
     MCYCLE,           // Machine cycle counter (lower 32 bits)
     MCYCLEH,          // Machine cycle counter (upper 32 bits)
-    MINSTRET,         // Machine instructions retired counter (lower 32 bits)
-    MINSTRETH,        // Machine instructions retired counter (upper 32 bits)
+    //MINSTRET,         // Machine instructions retired counter (lower 32 bits)
+    //MINSTRETH,        // Machine instructions retired counter (upper 32 bits)
     MCOUNTINHIBIT,    // Machine counter inhibit register
 % for pcount_num in range(ibex_config['MHPMCounterNum']):
     MHPMEVENT${pcount_num + 3},       // Machine performance monitoring event selector
@@ -135,6 +139,7 @@ const privileged_reg_t implemented_csr[] = {
     MHPMCOUNTER${pcount_num + 3}H,    // Machine performance monitoring counter (lower 32 bits)
 % endfor
 % if ibex_config['PMPEnable']:
+    MSECCFG,          // Machine security configuration register
     PMPCFG0,          // PMP configuration register
     PMPCFG1,          // PMP configuration register
     PMPCFG2,          // PMP configuration register
@@ -159,15 +164,15 @@ const privileged_reg_t implemented_csr[] = {
     DCSR,             // Debug control and status register
     DPC,              // Debug PC
     DSCRATCH0,        // Debug scratch register 0
-    DSCRATCH1,         // Debug scratch register 1
+    DSCRATCH1         // Debug scratch register 1
 % if ibex_config['DbgTriggerEn']:
-    TSELECT,         // Trigger select register
+    ,TSELECT,         // Trigger select register
     TDATA1,           // Trigger data register 1
     TDATA2,           // Trigger data register 2
-    TDATA3,           // Trigger data register 3
+    TDATA3            // Trigger data register 3
 % endif
-    MCONTEXT,         // Machine context register
-    SCONTEXT          // Supervisor context register
+    //MCONTEXT,         // Machine context register
+    //SCONTEXT          // Supervisor context register
 };
 
 // TODO: Co-simulation fix required so cpuctrl behaves correctly in co-sim for all ibex configs. For

dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml

@@ -35,6 +35,9 @@
   gen_opts: >
     +instr_cnt=10000
     +num_of_sub_program=5
+    +gen_all_csrs_by_default=1
+    +add_csr_write=MSTATUS,MEPC,MCAUSE,MTVAL
+    +no_csr_instr=0
   rtl_test: core_ibex_base_test
 
 - test: riscv_rand_jump_test