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https://github.com/lowRISC/ibex.git
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[DV] Enable aligned load/store test (#242)
* Add unaligned load/store test * Enable unaligned load/store test, remove obsolete files
This commit is contained in:
taoliug
udinator
parent
7eecbd1b05
commit
0e91a30496
6 changed files with 43 additions and 204 deletions
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@ -2,40 +2,41 @@
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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DV_DIR := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
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GEN_DIR := $(realpath ${DV_DIR}/../../vendor/google_riscv-dv)
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TOOLCHAIN := ${RISCV_TOOLCHAIN}
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OUT := "${DV_DIR}/out"
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DV_DIR := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
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GEN_DIR := $(realpath ${DV_DIR}/../../vendor/google_riscv-dv)
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TOOLCHAIN := ${RISCV_TOOLCHAIN}
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OUT := "${DV_DIR}/out"
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# Run time options for the instruction generator
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GEN_OPTS :=
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GEN_OPTS :=
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# Run time options for ibex RTL simulation
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SIM_OPTS :=
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SIM_OPTS :=
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# Enable waveform dumping
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WAVES := 1
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WAVES := 1
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# Enable coverage dump
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COV := 0
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COV := 0
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# RTL simulator
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SIMULATOR := "vcs"
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SIMULATOR := "vcs"
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# ISS (spike, ovpsim)
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ISS := "spike"
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ISS := "spike"
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# ISA
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ISA := "rv32imc"
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ISA := "rv32imc"
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# Test name (default: full regression)
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TEST := "all"
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TEST := "all"
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# Seed for instruction generator and RTL simulation
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SEED := -1
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SEED := -1
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# Verbose logging
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VERBOSE :=
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VERBOSE :=
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# Number of iterations for each test, assign a non-zero value to override the
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# iteration count in the test list
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ITERATIONS := 0
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ITERATIONS := 0
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# LSF CMD
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LSF_CMD :=
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LSF_CMD :=
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# Generator timeout limit in seconds
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TIMEOUT := 1800
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# Privileged CSR YAML description file
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CSR_FILE := ${DV_DIR}/riscv_dv_extension/csr_description.yaml
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CSR_FILE := ${DV_DIR}/riscv_dv_extension/csr_description.yaml
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# Pass/fail signature address at the end of test
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END_SIGNATURE_ADDR := 0x8ffffffc
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END_SIGNATURE_ADDR := 8ffffffc
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# Value written to END_SIGNATURE_ADDR that indicates test success
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PASS_VAL := 0x1
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# Value written to END_SIGNATURE_ADDR that indicates test failure
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@ -65,7 +66,7 @@ endif
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# Options used for privileged CSR test generation
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CSR_OPTS=--csr_yaml=${CSR_FILE} \
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--isa=${ISA} \
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--end_signature_addr=${END_SIGNATURE_ADDR}
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--end_signature_addr=0x${END_SIGNATURE_ADDR}
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# Generate random instructions
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.SILENT gen:
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@ -74,6 +75,7 @@ CSR_OPTS=--csr_yaml=${CSR_FILE} \
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python3 ./run.py \
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--o=${OUT}/instr_gen ${GEN_OPTS} \
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--steps=gen \
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--gen_timeout=${TIMEOUT} \
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--lsf_cmd="${LSF_CMD}" \
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${COMMON_OPTS} \
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${CSR_OPTS} \
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@ -89,6 +91,7 @@ gcc_compile:
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--o=${OUT}/instr_gen ${GEN_OPTS} \
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--steps=gcc_compile \
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${COMMON_OPTS} \
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--gcc_opts=-mno-strict-align \
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--isa=${ISA} \
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--mabi=ilp32
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@ -1,57 +0,0 @@
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#!/bin/bash
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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RUN_DIR="$1"
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report_file="$1/regr.log"
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rm -rf "$report_file"
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script_path="../../vendor/google_riscv-dv"
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compare_log () {
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spike_log="$1"
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ibex_log="$2"
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# -----------------------------------------------------------------------------
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# Convert spike log to standard instruction trace csv
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# -----------------------------------------------------------------------------
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# Remove all the init spike boot instructions
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# 0xffffffff80000080 is the first user instruction
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sed -i '/0xffffffff80000080/,$!d' "$spike_log"
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# Remove all instructions after ecall (end of program excecution)
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sed -i '/ecall/q' "$spike_log"
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# Convert the spike log to riscv_instr_trace.proto format
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spike_csv=$(echo "$spike_log" | sed 's/\.log/.csv/g')
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python $script_path/scripts/spike_log_to_trace_csv.py \
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--log $spike_log --csv $spike_csv >> $report_file
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# -----------------------------------------------------------------------------
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# Convert ibex log to standard instruction trace csv
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# -----------------------------------------------------------------------------
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# Remove all instructions after ecall (end of program excecution)
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sed -i '/ecall/q' "$ibex_log"
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# Convert the spike log to riscv_instr_trace.proto format
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ibex_csv=$(echo "$ibex_log" | sed 's/\.log/.csv/g')
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python ./riscv_dv_extension/ibex_log_to_trace_csv.py \
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--log $ibex_log --csv $ibex_csv >> $report_file
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# -----------------------------------------------------------------------------
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# Compare the trace log
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# -----------------------------------------------------------------------------
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python $script_path/scripts/instr_trace_compare.py $spike_csv $ibex_csv \
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"spike" "ibex" >> $report_file
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}
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echo "compare simulation result under $RUN_DIR"
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while read asm_test; do
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SRC=$(echo "$asm_test" | sed 's/^.*\///g' | sed 's/\.S>*$//g')
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echo "Test: $asm_test" >> $report_file
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compare_log $RUN_DIR/instr_gen/spike_sim/$SRC.S.o.log \
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$RUN_DIR/rtl_sim/$SRC/trace_core_00_0.log
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done <"$RUN_DIR/asm_test_list"
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passed_cnt="$(grep -c PASS $report_file)"
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failed_cnt="$(grep -c FAIL $report_file)"
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echo "$passed_cnt tests PASSED, $failed_cnt tests FAILED" >> $report_file
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cat $report_file
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@ -27,6 +27,8 @@ def process_ibex_sim_log(ibex_log, csv):
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trace_csv = RiscvInstructiontTraceCsv(csv_fd)
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trace_csv.start_new_trace()
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for line in f:
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if re.search("ecall", line):
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break
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# Extract instruction infromation
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m = re.search(r"^\s*(?P<time>\d+)\s+(?P<cycle>\d+) " \
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"(?P<pc>[0-9a-f]+) (?P<bin>[0-9a-f]+) (?P<instr>.*)" \
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@ -1,21 +0,0 @@
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// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//====================================================================
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// Test name : iterations : options
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//--------------------------------------------------------------------
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riscv_arithmetic_basic_test : 20 :
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riscv_machine_mode_rand_test : 20 :
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riscv_privileged_mode_rand_test : 0 :
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riscv_rand_instr_test : 20 :
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riscv_rand_jump_test : 20 :
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riscv_mmu_stress_test : 20 :
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riscv_page_table_exception_test : 0 :
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riscv_no_fence_test : 10 :
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riscv_sfence_exception_test : 0 :
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riscv_illegal_instr_test : 10 :
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riscv_hint_instr_test : 10 :
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riscv_ebreak_test : 20 :
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riscv_wfi_test : 5 : +enable_interrupt=1
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//--------------------------------------------------------------------
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@ -30,7 +30,7 @@
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- test: riscv_rand_instr_test
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description: >
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Random instruction stress test
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iterations: 20
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iterations: 10
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gen_test: riscv_instr_base_test
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gen_opts: >
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+instr_cnt=10000
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@ -58,7 +58,7 @@
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description: >
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Test with different patterns of load/store instructions, stress test MMU
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operations.
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iterations: 20
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iterations: 10
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gen_test: riscv_instr_base_test
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gen_opts: >
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+instr_cnt=10000
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@ -75,7 +75,7 @@
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instruction and handle corresponding exception properly. An exception
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handling routine is designed to resume execution after illegal
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instruction exception.
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iterations: 20
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iterations: 10
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gen_test: riscv_rand_instr_test
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gen_opts: >
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+enable_illegal_instruction=1
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@ -150,3 +150,18 @@
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no_iss: 1
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rtl_test: core_ibex_csr_test
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no_post_compare: 1
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- test: riscv_unaligned_load_store_test
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description: >
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Unaligned load/store test, ibex should handle it correctly without raising any exception
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iterations: 5
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gen_test: riscv_instr_base_test
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gen_opts: >
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+instr_cnt=10000
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+num_of_sub_program=5
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+directed_instr_0=riscv_load_store_rand_instr_stream,20
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+directed_instr_1=riscv_load_store_hazard_instr_stream,20
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+directed_instr_2=riscv_cache_line_stress_instr_stream,20
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+directed_instr_3=riscv_multi_page_load_store_instr_stream,20
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+enable_unaligned_load_store=1
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rtl_test: core_ibex_base_test
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103
dv/uvm/sim
103
dv/uvm/sim
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@ -1,103 +0,0 @@
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#!/usr/bin/env bash
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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# Script to run the assembly tests generated by the riscv-dv instruction generator.
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# Test directory
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RUN_DIR="./"
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# Assembly test file name
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TEST=""
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# Seed
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RAND_SEED=1
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SEED=""
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# Wavform dump options
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WAVES=0
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WAVES_OPTS=""
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# Coveragedump options
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COV=0
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COV_OPTS=""
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# Process command line options
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while [[ $# -gt 0 ]]
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do
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key="$1"
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case $key in
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-dir)
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RUN_DIR="$2"
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shift
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;;
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-test)
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TEST="$2"
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shift
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;;
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-waves)
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WAVES="$2"
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shift
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;;
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-cov)
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COV="$2"
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shift
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;;
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-seed)
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SEED="$2"
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RAND_SEED=0
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shift
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;;
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*)
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echo "unknown option $1"
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exit 1
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;;
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esac
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shift
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done
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# If the test is specified through "-test" option, run a single test rather
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# than all tests under RUN_DIR.
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if [[ $TEST == "" ]]; then
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find "$RUN_DIR" -name "*.S" > "$RUN_DIR/asm_test_list"
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else
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echo "$TEST" > "$RUN_DIR/asm_test_list"
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fi
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OUT="$RUN_DIR/rtl_sim"
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CWD=`pwd`
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# Run each test
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while read asm_test; do
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OPTS=""
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SRC=$(echo "$asm_test" | sed 's/^.*\///g' | sed 's/\.S>*$//g')
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BINFILE="$asm_test.bin"
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mkdir -p $OUT/$SRC
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cd $OUT/$SRC
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if [[ $RAND_SEED == 1 ]]; then
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SEED=$RANDOM
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fi
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if [[ $WAVES == 1 ]]; then
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WAVES_OPTS="-ucli -do $CWD/vcs.tcl"
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fi
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if [[ $COV == 1 ]]; then
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COV_OPTS="-cm line+tgl+assert+fsm+branch \
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-cm_dir ${RUN_DIR}/rtl_sim/test.vdb \
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-cm_log /dev/null \
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-assert nopostproc \
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-cm_name test_${SEED}"
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fi
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if [[ "$BINFILE" =~ "ebreak" ]]; then
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OPTS="+enable_debug_seq=1"
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fi
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if [[ "$BINFILE" =~ "wfi" ]]; then
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OPTS="+enable_irq_seq=1"
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fi
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CMD="$OUT/vcs_simv +UVM_TESTNAME=core_ibex_base_test \
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${WAVES_OPTS} +ntb_random_seed=${SEED} +vcs+lic+wait ${COV_OPTS}\
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+UVM_MAX_QUIT_COUNT=5 +bin=$BINFILE -l sim.log ${OPTS}"
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echo "Running simulation for : $CMD"
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$CMD
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done <"$RUN_DIR/asm_test_list"
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