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fixed ret and misaligned memory accesses
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parent
2d78d214de
commit
11f0e4556d
5 changed files with 8 additions and 7 deletions
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@ -325,7 +325,8 @@ module littleriscv_controller
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pc_set_o = 1'b1;
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exc_ack_o = 1'b1;
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exc_save_if_o = 1'b1;
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halt_id_o = 1'b1;
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exc_save_id_o = 1'b1;
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// we don't have to change our current state here as the prefetch
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// buffer is automatically invalidated, thus the next instruction
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@ -669,7 +669,7 @@ module littleriscv_id_stage
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.halt_id_o ( halt_id ),
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.misaligned_stall_o ( misaligned_stall ),
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.branch_2nd_stage_o ( branch_2nd_stage),
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.branch_2nd_stage_o ( branch_2nd_stage),
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.jr_stall_o ( jr_stall ),
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.load_stall_o ( load_stall ),
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@ -88,8 +88,8 @@ parameter INSTR_CSRRSI = { 17'b?, 3'b110, 5'b?, OPCODE_SYSTEM };
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parameter INSTR_CSRRCI = { 17'b?, 3'b111, 5'b?, OPCODE_SYSTEM };
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parameter INSTR_ECALL = { 12'b000000000000, 13'b0, OPCODE_SYSTEM };
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parameter INSTR_EBREAK = { 12'b000000000001, 13'b0, OPCODE_SYSTEM };
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parameter INSTR_ERET = { 12'b000100000000, 13'b0, OPCODE_SYSTEM };
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parameter INSTR_WFI = { 12'b000100000010, 13'b0, OPCODE_SYSTEM };
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parameter INSTR_ERET = { 12'b001100000010, 13'b0, OPCODE_SYSTEM };
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parameter INSTR_WFI = { 12'b000100000101, 13'b0, OPCODE_SYSTEM };
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// RV32M
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parameter INSTR_PMUL = { 7'b0000001, 10'b?, 3'b000, 5'b?, OPCODE_OP };
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@ -310,10 +310,10 @@ module littleriscv_load_store_unit
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else
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begin
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CS <= NS;
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if (ex_valid_i)
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if (ex_valid_i) begin
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data_misaligned_o <= data_misaligned;
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misaligned_addr_o <= data_addr_int;
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end
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if (data_rvalid_i && (~data_we_q))
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begin
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// if we have detected a misaligned access, and we are
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@ -741,7 +741,7 @@ module littleriscv_tracer
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// SYSTEM (others)
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INSTR_ECALL: trace.printMnemonic("ecall");
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INSTR_EBREAK: trace.printMnemonic("ebreak");
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INSTR_ERET: trace.printMnemonic("eret");
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INSTR_ERET: trace.printMnemonic("mret");
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INSTR_WFI: trace.printMnemonic("wfi");
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// PULP MULTIPLIER
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INSTR_PMUL: trace.printRInstr("p.mul");
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