fixed ret and misaligned memory accesses

This commit is contained in:
Pasquale Davide Schiavone 2017-01-18 16:25:31 +01:00
parent 2d78d214de
commit 11f0e4556d
5 changed files with 8 additions and 7 deletions

View file

@ -325,7 +325,8 @@ module littleriscv_controller
pc_set_o = 1'b1;
exc_ack_o = 1'b1;
exc_save_if_o = 1'b1;
halt_id_o = 1'b1;
exc_save_id_o = 1'b1;
// we don't have to change our current state here as the prefetch
// buffer is automatically invalidated, thus the next instruction

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@ -669,7 +669,7 @@ module littleriscv_id_stage
.halt_id_o ( halt_id ),
.misaligned_stall_o ( misaligned_stall ),
.branch_2nd_stage_o ( branch_2nd_stage),
.branch_2nd_stage_o ( branch_2nd_stage),
.jr_stall_o ( jr_stall ),
.load_stall_o ( load_stall ),

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@ -88,8 +88,8 @@ parameter INSTR_CSRRSI = { 17'b?, 3'b110, 5'b?, OPCODE_SYSTEM };
parameter INSTR_CSRRCI = { 17'b?, 3'b111, 5'b?, OPCODE_SYSTEM };
parameter INSTR_ECALL = { 12'b000000000000, 13'b0, OPCODE_SYSTEM };
parameter INSTR_EBREAK = { 12'b000000000001, 13'b0, OPCODE_SYSTEM };
parameter INSTR_ERET = { 12'b000100000000, 13'b0, OPCODE_SYSTEM };
parameter INSTR_WFI = { 12'b000100000010, 13'b0, OPCODE_SYSTEM };
parameter INSTR_ERET = { 12'b001100000010, 13'b0, OPCODE_SYSTEM };
parameter INSTR_WFI = { 12'b000100000101, 13'b0, OPCODE_SYSTEM };
// RV32M
parameter INSTR_PMUL = { 7'b0000001, 10'b?, 3'b000, 5'b?, OPCODE_OP };

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@ -310,10 +310,10 @@ module littleriscv_load_store_unit
else
begin
CS <= NS;
if (ex_valid_i)
if (ex_valid_i) begin
data_misaligned_o <= data_misaligned;
misaligned_addr_o <= data_addr_int;
end
if (data_rvalid_i && (~data_we_q))
begin
// if we have detected a misaligned access, and we are

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@ -741,7 +741,7 @@ module littleriscv_tracer
// SYSTEM (others)
INSTR_ECALL: trace.printMnemonic("ecall");
INSTR_EBREAK: trace.printMnemonic("ebreak");
INSTR_ERET: trace.printMnemonic("eret");
INSTR_ERET: trace.printMnemonic("mret");
INSTR_WFI: trace.printMnemonic("wfi");
// PULP MULTIPLIER
INSTR_PMUL: trace.printRInstr("p.mul");