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[rtl] Remove unused transition in ibex_controller FSM

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When in the FLUSH state we cannot have `csr_pipe_flush` set as it
depends upon `instr_executing` being set (within `ibex_id_stage`) and
that is only set in the DECODE stage.
This commit is contained in:
Greg Chadwick 2022-10-27 14:27:14 +01:00 • committed by Greg Chadwick
parent 5f5a70fca9
commit 2f9fd69ec4
3 changed files with 1 additions and 6 deletions
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1
doc/03_reference/coverage_plan.rst
View file

@ -193,7 +193,6 @@ Each pipeline stage has some associated state.
* ``FLUSH`` -> ``DECODE`` *
* ``FLUSH`` -> ``DBG_TAKEN_ID``
* ``FLUSH`` -> ``WAIT_SLEEP``
* ``FLUSH`` -> ``IRQ_TAKEN`` *
* ``FLUSH`` -> ``DBG_TAKEN_IF`` *
* ``WAIT_SLEEP`` -> ``SLEEP``
* ``SLEEP`` -> ``FIRST_FETCH``

3
dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
View file

@ -529,8 +529,7 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
bins out_of_flush0 = (FLUSH => DECODE);
bins out_of_flush1 = (FLUSH => DBG_TAKEN_ID);
bins out_of_flush2 = (FLUSH => WAIT_SLEEP);
bins out_of_flush3 = (FLUSH => IRQ_TAKEN);
bins out_of_flush4 = (FLUSH => DBG_TAKEN_IF);
bins out_of_flush3 = (FLUSH => DBG_TAKEN_IF);
bins out_of_wait_sleep = (WAIT_SLEEP => SLEEP);
bins out_of_sleep = (SLEEP => FIRST_FETCH);
// TODO: VCS does not implement default sequence so illegal_bins will be empty

3
rtl/ibex_controller.sv
View file

@ -809,9 +809,6 @@ module ibex_controller #(
csr_restore_dret_id_o = 1'b1;
end else if (wfi_insn) begin
ctrl_fsm_ns = WAIT_SLEEP;
end else if (csr_pipe_flush && handle_irq) begin
// start handling IRQs when doing CSR-related pipeline flushes
ctrl_fsm_ns = IRQ_TAKEN;
end
end // exc_req_q