github-mirrors/ibex
1
0
Fork 0
mirror of https://github.com/lowRISC/ibex.git synced 2025-04-20 11:57:12 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge branch 'newMul'

Browse source
This commit is contained in:
Pasquale Davide Schiavone 2017-06-01 16:00:33 +02:00
commit 36cd25c511
4 changed files with 19 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

4
zeroriscy_cs_registers.sv
View file

@ -167,8 +167,6 @@ module zeroriscy_cs_registers
case (csr_addr_i)
// mstatus: always M-mode, contains IE bit
12'h300: csr_rdata_int = {19'b0, mstatus_q.mpp, 3'b0, mstatus_q.mpie, 3'h0, mstatus_q.mie, 3'h0};
// mstatus
12'h300: csr_rdata_int = {
19'b0,
mstatus_q.mpp,
@ -317,8 +315,6 @@ module zeroriscy_cs_registers
assign PCCR_in[0] = 1'b1; // cycle counter
assign PCCR_in[1] = id_valid_i & is_decoding_i; // instruction counter
assign PCCR_in[2] = ld_stall_i & id_valid_q; // nr of load use hazards
assign PCCR_in[3] = jr_stall_i & id_valid_q; // nr of jump register hazards
assign PCCR_in[4] = imiss_i & (~pc_set_i); // cycles waiting for instruction fetches, excluding jumps and branches
assign PCCR_in[5] = mem_load_i; // nr of loads
assign PCCR_in[6] = mem_store_i; // nr of stores

5
zeroriscy_ex_block.sv
View file

@ -68,7 +68,7 @@ module zeroriscy_ex_block
output logic ex_ready_o // EX stage gets new data
);
localparam MULT_TYPE = 1; //0 is SLOW
localparam MULT_TYPE = 0; //0 is SLOW
logic [31:0] alu_result, multdiv_result;
@ -136,7 +136,8 @@ end
(
.clk ( clk ),
.rst_n ( rst_n ),
.multdiv_en_i ( multdiv_en ),
.mult_en_i ( mult_en_i ),
.div_en_i ( div_en_i ),
.operator_i ( multdiv_operator_i ),
.signed_mode_i ( multdiv_signed_mode_i ),
.op_a_i ( multdiv_operand_a_i ),

18
zeroriscy_multdiv_fast.sv
View file

@ -49,7 +49,7 @@ module zeroriscy_multdiv_fast
);
logic [ 4:0] div_counter_q, div_counter_n;
enum logic [2:0] {ALBL, ALBH, AHBL, AHBH, FINISH } mult_state_q, mult_state_n;
enum logic [1:0] {ALBL, ALBH, AHBL, AHBH } mult_state_q, mult_state_n;
enum logic [2:0] { MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH } divcurr_state_q, divcurr_state_n;
logic [34:0] mac_res_ext;
@ -71,6 +71,7 @@ module zeroriscy_multdiv_fast
logic [31:0] op_quotient_n;
logic [32:0] next_reminder, next_quotient;
logic [32:0] res_adder_h;
logic mult_is_ready;
always_ff @(posedge clk or negedge rst_n) begin : proc_mult_state_q
if(~rst_n) begin
@ -109,7 +110,7 @@ module zeroriscy_multdiv_fast
assign signed_mult = (signed_mode_i != 2'b00);
assign multdiv_result_o = mac_res_q[31:0];
assign multdiv_result_o = div_en_i ? mac_res_q[31:0] : mac_res_n[31:0];
assign mac_res_ext = $signed({sign_a, mult_op_a})*$signed({sign_b, mult_op_b}) + $signed(accum);
assign mac_res = mac_res_ext[33:0];
@ -249,7 +250,7 @@ module zeroriscy_multdiv_fast
endcase // divcurr_state_q
end
assign ready_o = (mult_state_q == FINISH) | (divcurr_state_q == MD_FINISH);
assign ready_o = mult_is_ready | (divcurr_state_q == MD_FINISH);
always_comb
begin : mult_fsm
mult_op_a = op_a_i[`OP_L];
@ -259,6 +260,7 @@ module zeroriscy_multdiv_fast
accum = mac_res_q;
mac_res_n = mac_res;
mult_state_n = mult_state_q;
mult_is_ready = 1'b0;
unique case (mult_state_q)
@ -304,7 +306,8 @@ module zeroriscy_multdiv_fast
MD_OP_MULL: begin
accum = {18'b0,mac_res_q[31:16]};
mac_res_n = {2'b0,mac_res[15:0],mac_res_q[15:0]};
mult_state_n = FINISH;
mult_is_ready = 1'b1;
mult_state_n = ALBL;
end
default: begin
accum = mac_res_q;
@ -325,12 +328,9 @@ module zeroriscy_multdiv_fast
accum[33:18] = {18{signed_mult & mac_res_q[33]}};
//result of AH*BL is not signed only if signed_mode_i == 2'b00
mac_res_n = mac_res;
mult_state_n = FINISH;
end
FINISH: begin
mult_state_n = ALBL;
//ready_o must not be a timing critical signal
mult_is_ready = 1'b1;
end
default:;

13
zeroriscy_multdiv_slow.sv
View file

@ -29,7 +29,8 @@ module zeroriscy_multdiv_slow
(
input logic clk,
input logic rst_n,
input logic multdiv_en_i,
input logic mult_en_i,
input logic div_en_i,
input logic [1:0] operator_i,
input logic [1:0] signed_mode_i,
input logic [31:0] op_a_i,
@ -76,7 +77,7 @@ module zeroriscy_multdiv_slow
begin
alu_operand_a_o = accum_window_q;
multdiv_result_o = accum_window_q[31:0];
multdiv_result_o = div_en_i ? accum_window_q[31:0] : res_adder_l;
unique case(operator_i)
@ -174,7 +175,7 @@ module zeroriscy_multdiv_slow
curr_state_q <= MD_IDLE;
op_numerator_q <= '0;
end else begin
if(multdiv_en_i) begin
if(mult_en_i | div_en_i) begin
unique case(curr_state_q)
MD_IDLE: begin
@ -255,11 +256,11 @@ module zeroriscy_multdiv_slow
unique case(operator_i)
MD_OP_MULL: begin
accum_window_q <= res_adder_l;
curr_state_q <= MD_FINISH;
curr_state_q <= MD_IDLE;
end
MD_OP_MULH: begin
accum_window_q <= res_adder_l;
curr_state_q <= MD_FINISH;
curr_state_q <= MD_IDLE;
end
MD_OP_DIV: begin
//this time we save the quotient in accum_window_q since we do not need anymore the reminder
@ -295,7 +296,7 @@ module zeroriscy_multdiv_slow
end
assign ready_o = curr_state_q == MD_FINISH;
assign ready_o = (curr_state_q == MD_FINISH) | (curr_state_q == MD_LAST & (operator_i == MD_OP_MULL | operator_i == MD_OP_MULH));
endmodule // zeroriscy_mult