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Fix bugs introduced in the last two commits

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This commit is contained in:
Andreas Traber 2015-11-30 15:13:08 +01:00
parent 965be8059a
commit 371a211be7
2 changed files with 2 additions and 2 deletions
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2
if_stage.sv
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@ -302,7 +302,7 @@ module riscv_if_stage
// next instruction will be aligned
fetch_ready = 1'b1;
if (is_compressed[1])
if (is_compressed[0])
offset_fsm_ns = WAIT_ALIGNED;
else
offset_fsm_ns = WAIT_UNALIGNED;

2
prefetch_buffer.sv
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@ -72,7 +72,7 @@ module riscv_fetch_fifo
assign out_valid_o = (rdata_valid_Q[0] || (addr_valid_Q[0] && in_rdata_valid_i));
assign out_unaligned_rdata_o = (rdata_valid_Q[1]) ? {rdata_Q[1][15:0], rdata_Q[0][31:16]} : {in_rdata_i[15:0], rdata_Q[0][31:16]};
assign out_unaligned_rdata_o = (rdata_valid_Q[1]) ? {rdata_Q[1][15:0], out_rdata_o[31:16]} : {in_rdata_i[15:0], out_rdata_o[31:16]};
// it is implied that rdata_valid_Q[0] is set
assign out_unaligned_valid_o = (rdata_valid_Q[1] || (addr_valid_Q[1] && in_rdata_valid_i));