fix syntax issues raised by Altera Quartus

zeroriscy_alu.sv

@@ -54,7 +54,7 @@ module zeroriscy_alu
   generate
     genvar k;
     for(k = 0; k < 32; k++)
-    begin
+    begin : g_revloop
       assign operand_a_rev[k] = operand_a_i[31-k];
     end
   endgenerate 
@@ -148,7 +148,7 @@ module zeroriscy_alu
   genvar       j;
   generate
     for(j = 0; j < 32; j++)
-    begin
+    begin : g_resrevloop
       assign shift_left_result[j] = shift_right_result[31-j];
     end
   endgenerate

zeroriscy_core.sv

@@ -172,6 +172,7 @@ module zeroriscy_core
   logic        id_ready;
   logic        ex_ready;
 
+  logic        if_valid;
   logic        id_valid;
   logic        wb_valid;
 

zeroriscy_cs_registers.sv

@@ -159,8 +159,7 @@ module zeroriscy_cs_registers
   // read logic
   always_comb
   begin
-    csr_rdata_int = '0;
-
+	 csr_rdata_int = '0;
     case (csr_addr_i)
 
       // mstatus: always M-mode, contains IE bit
@@ -182,7 +181,8 @@ module zeroriscy_cs_registers
 
       // mhartid: unique hardware thread id
       12'hF14: csr_rdata_int = {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]};
-
+		
+		default: ;
     endcase
   end
 
@@ -207,7 +207,7 @@ module zeroriscy_cs_registers
       12'h341: if (csr_we_int) mepc_n = csr_wdata_int;
       // mcause
       12'h342: if (csr_we_int) mcause_n = {csr_wdata_int[31], csr_wdata_int[4:0]};
-
+		default: ;
     endcase
 
     // exception controller gets priority over other writes
@@ -325,8 +325,8 @@ module zeroriscy_cs_registers
   // assign external performance counters
   generate
     genvar i;
-    for(i = 0; i < N_EXT_CNT; i++)
-    begin
+    for (i = 0; i < N_EXT_CNT; i++) 
+    begin : g_extcounters
       assign PCCR_in[N_PERF_COUNTERS - N_EXT_CNT + i] = ext_counters_i[i];
     end
   endgenerate

zeroriscy_debug_unit.sv

@@ -326,6 +326,7 @@ module zeroriscy_debug_unit
       RD_GPR:  debug_rdata_o = regfile_rdata_i;
       RD_DBGA: debug_rdata_o = dbg_rdata;
       RD_DBGS: debug_rdata_o = dbg_rdata;
+		default: ;
     endcase
   end
 

zeroriscy_ex_block.sv

@@ -83,7 +83,7 @@ module zeroriscy_ex_block
   At synthesis time, all the combinational and sequential logic
   from the multdiv_i module are eliminated
 */
-
+generate
 if (RV32M) begin
   assign multdiv_en_sel     = MULT_TYPE == 0 ? mult_en_i | div_en_i : div_en_i;
   assign multdiv_en         = mult_en_i | div_en_i;
@@ -91,6 +91,7 @@ end else begin
   assign multdiv_en_sel     = 1'b0;
   assign multdiv_en         = 1'b0;
 end
+endgenerate
 
   assign regfile_wdata_ex_o = multdiv_en ? multdiv_result : alu_result;
 
@@ -131,6 +132,7 @@ end
   //                                                            //
   ////////////////////////////////////////////////////////////////
 
+  generate
   if (MULT_TYPE == 0) begin : multdiv_slow
     zeroriscy_multdiv_slow multdiv_i
     (
@@ -170,6 +172,7 @@ end
      .multdiv_result_o   ( multdiv_result        )
     );
   end
+  endgenerate
 
   always_comb
   begin

zeroriscy_fetch_fifo.sv

@@ -136,10 +136,11 @@ module zeroriscy_fetch_fifo
   // FIFO management
   //////////////////////////////////////////////////////////////////////////////
 
-  int j;
   always_comb
   begin
-    addr_int    = addr_Q;
+    int j;
+	 
+	 addr_int    = addr_Q;
     rdata_int   = rdata_Q;
     valid_int   = valid_Q;
     

zeroriscy_load_store_unit.sv

@@ -468,6 +468,7 @@ module zeroriscy_load_store_unit
           if(data_addr_int[1:0] == 2'b11)
             data_misaligned = 1'b1;
         end
+		  default: ;
       endcase // case (data_type_ex_i)
     end
   end

zeroriscy_register_file_ff.sv

@@ -56,7 +56,7 @@ module zeroriscy_register_file
 
 );
 
-  localparam    ADDR_WIDTH = RV32E ? 4 : 5;;
+  localparam    ADDR_WIDTH = RV32E ? 4 : 5;
   localparam    NUM_WORDS  = 2**ADDR_WIDTH;
 
   logic [NUM_WORDS-1:0][DATA_WIDTH-1:0] rf_reg;